Power conservation with a synchronous master-slave serial data bus

A system comprising a master device communicatively coupled to a serial synchronous communications line, said communications line defining a clock line and data line, each of said clock and data lines biased high, said master having a clock line driver actuable to pull the clock line low, said master having a respective data line driver actuable to pull the data line low;

• said master device disposed to operate at a first power level and at a second power level;
• said system further comprising a latch comprising a line driver actuable to pull the clock line low, said latch responsive to said master device being at said second power level, and responsive to said clock line transitioning to a low level, for actuating its line driver thereby holding the clock line low;
• said latch further responsive to said master device reaching its first power level for deactuating the line driver of the latch.

A system comprising a master device and first and second slave devices, each slave device communicatively coupled with the master device by a respective serial synchronous communications line, each said communications line defining a clock line and a data line, each of said clock and data lines biased high, each of said master and slave having a respective clock line driver actuable to pull the respective clock line low, each of said master and slave having a respective data line driver actuable to pull the respective data line low;

• said master device disposed to operate at a first power level and at a second lower power level;
• said system further comprising first and second latches corresponding to respective slave devices, each said latch comprising a line driver actuable to pull a respective clock line low, each said latch responsive to said master device being at said second power level, and responsive to said respective clock line transitioning to a low level, for actuating its line driver thereby holding the respective clock line low;
• each said latch further responsive to said master device reaching its first power level for deactuating the line driver of the latch.

A system comprising a master device communicatively coupled to first and second serial synchronous communications lines, each said communications line defining a respective clock line and a respective data line, each of said clock and data lines biased high, said master having respective clock line drivers actuable to pull the respective clock lines low, said master having respective data line drivers actuable to pull the respective data lines low;

• said master device disposed to operate at a first power level and at a second lower power level;
• said system further comprising first and second latches corresponding to the first and second communications lines, each latch comprising a respective line driver actuable to pull the respective clock line low, each said latch responsive to said master device being at said second power level, and responsive to said respective clock line transitioning to a low level, for actuating its respective line driver thereby holding the respective clock line low;
• each said latch further responsive to said master device reaching its first power level for deactuating the respective line driver of the latch.