System and method for low-noise control of radio frequency devices

A control bus for providing a communication interconnect path between a bus master and one or more bus slaves, wherein the bus master is coupled to a processor and each bus slave is coupled to an RF device that operates without a free-running clock, the control bus comprising:

• a first data line coupled to the bus master and to the one or more bus slaves;
• a second data line coupled to the bus master and to the one or more bus slaves;
• a first clock line, coupled to the bus master and to the one or more bus slaves, to be asserted by the bus master when transmitting serial data to the one or more bus slaves via said first data line or receiving serial data from the one or more bus slaves via said second data line;
• and
• a second clock line, coupled to the bus master and to the one or more bus slaves, to be asserted by the one or more bus slaves when transmitting serial data to the bus master via said second data line.

A system for RF control, comprising:

• a processor;
• a bus master coupled to said processor;
• a bus slave;
• an RF device coupled to said bus slave;
• and
• an RF control bus, including:
• a bi-directional data line coupled to said bus master and to said bus slave,
• a first clock line, coupled to said bus master and to said bus slave, to be asserted by said bus master when transmitting serial data to or receiving serial data from said bus slave via said bi-directional data line, and
• a second clock line, coupled to said bus master and to said bus slave, to be asserted by said bus slave when transmitting serial data to said bus master via said bi-directional data line.

A method of controlling an RF device, wherein an RF control bus interconnects a bus master and a bus slave, wherein the bus slave is coupled to the RF device and the bus master is coupled to a processor, and wherein the RF control bus includes a data line, a first clock line, and a second clock line, comprising the steps of:

• (a) sending a parallel transmit message from the processor to the bus master;
• (b) converting the parallel transmit message into a serial data stream;
• (c) formatting said serial data stream according to a serial message format, thereby creating a formatted message;
• (d) sending a synchronization burst to the bus slave via the data line;
• (e) asserting the first clock line while sending said formatted message from the bus master to the bus slave via the data line;
• and
• (f) determining whether the bus slave is the intended recipient of said formatted message, and if so, formatting a status message and asserting the first and second clock lines while sending said status message from the bus slave to the bus master via the data line.