US 6,557,053 B1 · Queue manager for a buffer

Abstract

A bandwidth conserving queue manager for a FIFO buffer is provided, preferably on an ASIC chip and preferably including separate DRAM storage that maintains a FIFO queue which can extend beyond the data storage space of the FIFO buffer to provide additional data storage space as needed. FIFO buffers are used on the ASIC chip to store and retrieve multiple queue entries. As long as the total size of the queue does not exceed the storage available in the buffers, no additional data storage is needed. However, when some predetermined amount of the buffer storage space in the FIFO buffers is exceeded, data are written to and read from the additional data storage, and preferably in packets which are of optimum size for maintaining peak performance of the data storage device and which are written to the data storage device in such a way that they are queued in a first-in, first-out (FIFO) sequence of addresses. Preferably, the data are written to and are read from the DRAM in burst mode.

Claims12

Dependent claims

A queue manager for managing data input to a system from an outside source, comprising:

an input FIFO buffer for receiving and storing data items from said outside source;
an output FIFO buffer for receiving, storing and outputting data items to said system;
a memory storage device interfacing with said input FIFO buffer, and said output FIFO buffer, and a control mechanism to selectively write data from said input FIFO buffer to said memory storage device, and read data from said memory storage device to said output FIFO buffer;
wherein said control mechanism includes logic to connect said input FIFO buffer to said output FIFO buffer until said output FIFO buffer is filled to a first predetermined amount and said input FIFO buffer is filled to a second predetermined amount, and thereafter connect said input FIFO buffer to said memory storage device until said memory storage device is empty and said output FIFO buffer is empty, and then connect said input FIFO buffer to said output FIFO buffer.

1 more element

Dependencies are inferred from the claim text.

Queue manager for a buffer

Life of this patent

Queue manager for a buffer

Life of this patent

Abstract

Claims12