Computer system implementing a system and method for ordering input/output (IO) memory operations within a coherent portion thereof

The computer system as recited in claim 6, wherein the first transaction is a posted write transaction for storing data within the memory.

A node comprising:

• a plurality of interface logic circuits, each of said plurality of interface logic circuits for coupling to a respective link, at least one of said respective links being a non-coherent link and remaining links being coherent links;
• and
• a host bridge coupled to receive a first transaction from the non-coherent link and a subsequent second transaction from the non-coherent link, wherein the host bridge is configured to generate a third transaction corresponding to the first transaction for transmission on one of the coherent links, and wherein the host bridge is configured to generate a fourth transaction corresponding to the second transaction for transmission on one of the coherent links dependent on a progress of the third transaction and a predetermined set of ordering rules.

A node comprising:

• a plurality of interface logic circuits, each of said plurality of interface logic circuits for coupling to a respective link, at least one of said respective links being a non-coherent link and remaining links being coherent links;
• and
• a host bridge coupled to receive a first transaction from the non-coherent link and a subsequent second transaction from the non-coherent link, wherein the host bridge is configured to generate a third transaction corresponding to the first transaction for transmission on one of the coherent links, and wherein the host bridge is configured to permit completion of the second transaction on the non-coherent link dependent on a progress of the third transaction and a predetermined set of ordering rules.

A node comprising:

• a plurality of interface logic circuits, each of said plurality of interface logic circuits for coupling to a respective link, at least one of said respective links being a non-coherent link and remaining links being coherent links;
• and
• a host bridge coupled to receive a first transaction from the non-coherent link and a subsequent second transaction from the non-coherent link, wherein the host bridge is configured to generate a third transaction corresponding to the first transaction for transmission on one of the coherent links, and wherein the host bridge is configured to monitor progress of the third transaction and is configured to control progress of the second transaction responsive to the progress of the third transaction according to a predetermined set of order rules.

The node as recited in clam 26 wherein the host bridge is configured generate a fourth transaction corresponding to the second transaction for transmission on one of the coherent links, and wherein the host bridge is configured to cause the transmission of the fourth transaction responsive to the progress of the third transaction according to the predetermined set of ordering rules.

A computer system comprising:

• a plurality of nodes interconnected using coherent links, wherein at least a first node of the plurality of nodes comprises a host bridge;
• and
• at least one non-coherent node coupled to the first node via a non-coherent link, wherein the non-coherent node is configured to transmit a first transaction and a subsequent second transaction to the first node on the non-coherent link, and wherein the host bridge is configured to generate a third transaction corresponding to the first transaction for transmission on one of the coherent links, and wherein the host bridge is configured to monitor progress of the third transaction and is configured to control progress of the second transaction responsive to the progress of the third transaction according to a predetermined set of ordering rules.