Rounding anticipator for floating point operations

A rounding anticipation system that operates in parallel with a normalizer in a floating point arithmetic system, where the normalizer includes a coarse shifter having a coarse shift output, a medium shifter having a medium shift output and a medium shift select signal, and a fine shifter having a fine shift output and a fine shift select signal, comprising:

• a first logic level, said first logic level accepts the coarse shift output from the normalizer and encodes coarse propagation information for a plurality of preselected coarse propagation bit groups;
• a second logic level, said second logic level derives propagation information for preselected groups of bit positions of the medium shift output of the normalizer by selectively combining said coarse propagation information from coarse propagation bit groups selected according to the value of the medium shift select signal from the normalizer;
• a third logic level, said third logic level derives top bit, middle bit, and bottom bit propagation information for a plurality of preselected top groups, middle groups, and bottom groups of bit positions of the medium shift output as a function of the value of the fine shift select signal by selectively combining said propagation information from said second logic level with medium shift output bit values;
• and
• a fourth logic level, said fourth logic level produces an incremented, normalized intermediate mantissa result by combining fine shift output bit values with said top bit propagation information, said middle bit propagation information, and said bottom bit propagation information for the top group of bit positions, the middle group of bit positions, and the bottom group of positions that correspond to said fine shift output bit values.

A method of incrementing an intermediate mantissa result while it is being normalized in a floating point arithmetic system that includes a normalizer with a coarse shifter having a coarse shift output, a medium shifter having a medium shift output and a medium shift select signal, and a fine shifter having a fine shift output and a fine shift select signal, comprising:

• accepting the coarse shift output from the normalizer and encoding coarse propagation information for a plurality of preselected coarse propagation bit groups of said coarse shift output;
• deriving medium propagation information for preselected groups of bit positions of the medium shift output of the normalizer by selectively combining said coarse propagation information from coarse propagation bit groups selected according to the value of the medium shift select signal from the normalizer;
• deriving top bit, middle bit, and bottom bit propagation information for a plurality of preselected top groups, middle groups, and bottom groups of bit positions of the medium shift output as a function of the value of the fine shift select signal by selectively combining said medium propagation information with medium shift output bit values;
• and
• producing an incremented, normalized intermediate mantissa result by combining fine shift output bit values with said top bit propagation information, said middle bit propagation information, and said bottom bit propagation information for the top group of bit positions, the middle group of bit positions, and the bottom group of positions that correspond to said fine shift output bit values.

A method of making a rounding anticipator that operates in parallel with the normalizer in a floating point arithmetic system where the normalizer includes a coarse shifter having a coarse shift output, a medium shifter having a medium shift output and a medium shift select signal, and a fine shifter having a fine shift output and a fine shift select signal, comprising:

• providing a first logic level that accepts the coarse shift output from the normalizer and encodes coarse propagation information for a plurality of preselected coarse propagation bit groups;
• providing a second logic level that derives propagation information for preselected groups of bit positions of the medium shift output of the normalizer by selectively combining said coarse propagation information from coarse propagation bit groups selected according to the value of the medium shift select signal from the normalizer;
• providing a third logic level that derives top bit, middle bit, and bottom bit propagation information for a plurality of preselected top groups, middle groups, and bottom groups of bit positions of the medium shift output as a function of the value of the fine shift select signal by selectively combining said propagation information from said second logic level with medium shift output bit values;
• and
• providing a fourth logic level, said fourth logic level produces an incremented, normalized intermediate mantissa result by combining fine shift output bit values with said top bit propagation information, said middle bit propagation information, and said bottom bit propagation information for the top group of bit positions, the middle group of bit positions, and the bottom group of positions that correspond to said fine shift output bit values.