Timing calibration method and semiconductor device testing apparatus having timing calibration function

A timing calibration method in a semiconductor device testing apparatus comprising a plurality of test pattern signal transmission paths through which test pattern signals are transmitted to output pins and testing a semiconductor device under test using the thus transmitted test pattern signals,

• said timing calibration method comprising the steps of:
• selectively connecting the respective output pins one after another to a timing measurement device through respective pin selection paths which are provided to correspond to the output pins, respectively;
• measuring by means of the timing measurement device signal propagation delay time values through the respective pin selection paths and storing the measured values in a memory;
• determining one of the output pins as a reference output pin and calculating deviation values between the delay time value as a reference value through the pin selection path for the reference output pin and respective delay time values through remaining pin selection paths for remaining output pins other than the reference output pin;
• measuring by means of the timing measurement device total signal propagation delay time vales through respective series connections each of which is constituted of one of the test pattern signal transmission paths and one of the pin selection paths
• calculating deviation values between the total signal propagation delay time value for the reference output pin and the respective total signal propagation delay time values;
• and
• adjusting signal propagation delay time values of timing calibrators in the respective test pattern signal transmission paths for the remaining output pins such that those deviation values of the total delay time values for the respective remaining output pins accord with the corresponding deviation values, respectively, thereby calibrating differences in signal propagation delay time values of the respective test pattern signal transmission paths.

A semiconductor device testing apparatus wherein a semiconductor device under test coupled to output pins is tested by using test pattern signals transmitted to the output pins, said testing apparatus comprising:

• a plurality of test pattern signal transmission paths each constituted of a series connection of a waveform formatter, a timing calibrator, a driver and one of the output pins, respectively,
• a computer system controlling operations of the testing apparatus;
• a timing measurement device used for timing calibration mode;
• and
• a pin selection device used for timing calibration mode and forming pin selection paths which selectively connect the output pins one by one to the timing measurement device, wherein
• said timing measurement device measures total signal propagation delay time values (T1, T2, - - - ) of timing calibration pulse signals transmitted through respective series connections of one of the respective signal transmission paths and one of the respective pin selection paths for the respective output pins,
• said computer system includes:
• memory means for storing therein delay time values (TA1, TA2, - - - ) of the timing calibration pulse signal transmitted through the respective pin selection paths;
• subtract means for subtracting the stored delay time values (TA1, TA2, - - - ) through the respective pin selection paths stored in the memory means from the corresponding measured total delay time values (T1, T2, - - - ) through the respective pin channels;
• and
• timing control means for controlling the delay time values of respective timing calibrators such that difference delay time values (TX1, TX2, - - - ) for the respective output pins obtained as results of the subtract means are converged to a same predetermined constant value (TX1′, TX2′, - - - ,=TC).

A semiconductor device testing apparatus wherein a semiconductor device under test coupled to output pins is tested by using test pattern signals transmitted to the output pins, said testing apparatus comprising:

• a plurality of test pattern signal transmission paths each constituted of a series connection of a waveform formatter, a timing calibrator, a driver and one of the output pins, respectively,
• a computer system controlling operations of the testing apparatus;
• a timing measurement device used for timing calibration mode;
• and
• a pin selection device used for timing calibration mode and forming pin selection paths which selectively connect the output pins one by one to the timing measurement device, wherein
• said timing measurement device measures total signal propagation delay time values (T1, T2, - - - ) of timing calibration pulse signals transmitted through respective series connections of one of the respective signal transmission paths and one of the respective pin selection paths for the respective output pins,
• said computer system includes:
• memory means for storing therein delay time values (TA1, TA2, - - - ) of the timing calibration pulse signal transmitted through the respective pin selection paths;
• calculation means for calculating deviation values (ΔT1, ΔT2, - - - ) between the stored delay time value (TA1) for one of the output pins determined as a reference output pin and respective stored delay time values (TA2, TA3, - - - ) through remaining pin selection paths for the remaining output pins other than the reference output pin;
• and
• timing control means for adjusting delay time values of the respective timing calibrators such that those respective deviation delay time values (T2−T1, T3−T1, - - - ) between the total signal propagation delay time value (T1) through a total signal path which is constituted of a series connection of the test pattern signal transmission path and the pin selection path for the reference output pin and the respective total signal propagation delay time values (T2, T3, - - - ) through respective total signal paths which are constituted of series connections of the test pattern signal transmission paths and the pin selection paths for remaining output pins other than the reference output pin, accord with the corresponding deviation delay time values (ΔT1=T2−T1, ΔT2=T3−T1, - - - ) through the respective pin selection paths for the remaining output pins, respectively.