On-the-fly compression for pixel data
AssigneeTeleman Multimedia, Inc.
InventorSuk Hyun Hong
Life of this patent
Estimating the term…
Abstract
A video signal processor operates an arithmetic logic unit to perform on-the-fly compression of image data as the image data is input to the processor. The on-the-fly compression provides a data input pipeline that stores compressed image data for a large image area in a relatively small buffer in the processor. A hierarchical motion estimation process can first search the large image area by comparing blocks of the compressed image data to a compressed reference block. The hierarchical search process can then store uncompressed image data for a smaller image area and search the smaller image area to accurately determine a motion vector for the reference block.
Claims4
A method for operating a processor, comprising:
- receiving pixel data for an image array, at an input port of the processor;
- directing the pixel data through an arithmetic logic unit;
- performing in the arithmetic logic unit an on-the-fly compression process that converts the pixel data to compressed pixel data as the pixel data are input through the input port;
- storing the compressed pixel data in a buffer of the processor;
- searching the compressed pixel data in the buffer for a block of the compressed pixel data that best matches a compressed reference block;
- loading into the processor an uncompressed block of pixel data that corresponds to a portion of an image including an image area that corresponds to the block of the compressed pixel data that best matches a compressed reference block;
- and
- searching the uncompressed block of pixel data for a block of the uncompressed pixel data that best matches a reference block.
A method for operating a processor, comprising:
- receiving pixel values for an image array, at an input port of the processor;
- directing the pixel values into an arithmetic logic unit as the processor receives the pixel values;
- operating the arithmetic logic unit to combine pixel values of the image array to generate compressed pixel values, the arithmetic logic unit operating on the pixel values at a rate matching a rate at which the input port receives the pixel values;
- storing the compressed pixel values in a buffer of the processor to construct a compressed image array;
- searching the compressed pixel values in the buffer for a block of the compressed pixel values that best matches a compressed reference block;
- loading into the processor an uncompressed block of pixel values that correspond to a portion of an image including an image area that corresponds to the block of the compressed pixel values that best matches a compressed reference block;
- and
- searching the uncompressed block of pixel values for a block of the uncompressed pixel values that best matches a reference block.
Dependencies are inferred from the claim text.