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AssigneeNational Semiconductor Corporation
InventorKarthik Reddy Neravetla
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An apparatus and method is disclosed for providing a phase locked loop clock divider circuit utilizing a high speed linear feedback shift register with a two stage pipeline in its feedback path. A plurality of “pre-load” flip flop (PLFF) circuits and multiplexers are coupled to a plurality of linear feedback shift register (LFSR) flip flop circuits and multiplexers. The PLFF circuits hold pre-calculated initial LFSR sequence values to be loaded into the LFSR flip flop circuits. The load enable signal to the PLFF multiplexers and to the LFSR multiplexers is low for three successive input clock cycles. The present invention is capable of operating at high frequencies due to a shortened timing critical feedback path.
A linear feedback shift register of the type comprising a plurality of linear feedback shift register (LFSR) flip flop circuits and a plurality of linear feedback shift register (LFSR) multiplexers alternately coupled together, where an input of each LFSR flip flop circuit is coupled to an output of an LFSR multiplexer, and where an output of each LFSR flip flop circuit may be provided to an input of an LFSR multiplexer, said linear feedback shift register comprising:
A phase locked loop clock divider circuit comprising a linear feedback shift register of the type comprising a plurality of linear feedback shift register (LFSR) flip flop circuits and a plurality of linear feedback shift register (LFSR) multiplexers alternately coupled together, where an input of each LFSR flip flop circuit is coupled to an output of an LFSR multiplexer, and where an output of each LFSR flip flop circuit may be provided to an input of an LFSR multiplexer, said linear feedback shift register comprising:
A method for providing a linear feedback shift register having n bits where n is an integer, said method comprising the steps of:
Dependencies are inferred from the claim text.