Shift register

A shift register having a plurality of stages which are connected to a high level voltage source, a low level voltage source and a phase-delayed clock signal generator, wherein the stages are connected to corresponding row lines and are connected in cascade with respect to a scanning signal for charging and discharging the row lines, each one of the stages comprising:

• output circuit means including a pull-up transistor and a pull-down transistor, said pull-up transistor having
• a first input electrode responsive to a first clock signal having a delayed phase in comparison to the scanning signal,
• a first output electrode connected to the row line, and
• a first control electrode;
• said pull-down transistor having
• a second input electrode connected to the low level voltage source,
• a second output electrode connected to the row line, and
• a second control electrode;
• input circuit means being responsive to the scanning signal for generating a first control signal to be applied to the first control electrode, and responsive to a second clock signal having a delayed phase in comparison to the first clock signal for generating a second control signal to be applied to the second control electrode;
• means external to said pull-up transistor for raising a voltage for the first control signal;
• and
• means for discharging the second control signal during a time interval when the first control signal is enabled.

A shift register having a plurality of stages which are connected to a high level voltage source, a low level voltage source and a phase-delayed clock signal generator, wherein the stages are connected to corresponding row lines and are connected in cascade with respect to a scanning signal for charging and discharging the row lines, each one of the stages comprising:

• output circuit device including a pull-up transistor and a pull-down transistor, said pull-up transistor having a first input electrode for receiving a first clock signal having a delayed phase in comparison to the scanning signal, a first output electrode connected to the raw line, and a first control electrode;
• said pull-down transistor having a second input electrode connected to the low level voltage source, a second output electrode connected to the row line, and a second control electrode;
• input circuit device being responsive to the scanning signal for generating a first control signal to be applied to the first control electrode, and responsive to a second clock signal having a delayed phase in comparison to the scanning signal for generating a second control signal to be applied to the second control electrode;
• means for raising a voltage of the first control signal;
• and
• means for accelerating a discharging speed at the row line.

A shift register for driving gate lines of liquid crystal display and responsive to a scanning signal, a first voltage source and a second voltage source, the shift register comprising:

• a plurality of stages, each stage including
• output circuit device including a pull-up transistor and a pull-down transistor, the pull-up transistor having a first control electrode, a first input electrode coupled to a first clock signal having a delayed phase in comparison to the scanning signal and a first output electrode connected to a gate line;
• said pull-down transistor having a second control electrode, a second input electrode coupled to the second voltage source and a second output electrode connected to the gate line;
• input circuit device responsive to the scanning signal for generating a first control signal to be applied to the first control electrode, and responsive to a second clock signal having a delayed phase in comparison to the scanning signal for generating a second control signal to be applied to the second control electrode;
• and
• a voltage controller coupled between the first control electrode and the gate line to raise a voltage of the first control signal.

A shift register for driving gate lines of liquid crystal display and responsive to a scanning signal, a first voltage source and a second voltage source, the shift register comprising:

• a plurality of stages, each stage including
• output circuit device including a pull-up transistor and a pull-down transistor, the pull-up transistor having a first control electrode, a first input electrode coupled to a first clock signal having a delayed phase in comparison to the scanning signal and a first output electrode connected to a gate line;
• said pull-down transistor having a second control electrode, a second input electrode coupled to the second voltage source and a second output electrode connected to the gate line;
• input circuit device responsive to the scanning signal for generating a first control signal to be applied to the first control electrode, and responsive to a second clock signal having a delayed phase in comparison to the first clock signal for generating a second control signal to be applied to the second control electrode;
• a voltage controller coupled between the first control electrode and the gate line to raise a voltage of the first control signal;
• and
• a discharging device responsive to the first control signal to discharge the second control signal.

A shift register for a driving gate lines of liquid crystal display and responsive to a scanning signal, a first voltage source and a second voltage source, the shift register comprising:

• a plurality of stages, each stage including
• output circuit device including a pull-up transistor and a pull-down transistor, the pull-up transistor having a first control electrode, a first input electrode coupled to a first clock signal having a delayed phase in comparison to the scanning signal and a first output electrode connected to a gate line;
• said pull-down transistor having a second control electrode, a second input electrode coupled to the second voltage source and a second output electrode connected to the gate line;
• input circuit device responsive to the scanning signal for generating a first control signal to be applied to the first control electrode, and responsive to a second clock signal having a delayed phase in comparison to the scanning signal for generating a second control signal to be applied to the second control electrode;
• a voltage controller coupled between the first control electrode and the gate line to raise a voltage of the first control signal;
• a first discharging device responsive to the scanning signal to discharge the second control signal;
• and
• a second discharging device coupled to the gate line.