Multi-bit counter
AssigneeHynix Semiconductor Inc.
InventorSaeng-Hwan Kim
Life of this patent
Estimating the term…
Abstract
A multi-bit counter of the present invention is capable of high-speed operation because the time needed for increasing count values and combining count bits for a carry can be minimized by presetting all bit combinations for a unit having multiple bits and selecting the preset combinations by a clock signal, i.e., by presetting the state of each of the bit combinations and outputting a next required value.
Claims27
A multi-bit counter comprising a multiplicity of unit counters, each for receiving bit combinations of a unit external address signal, setting an external input by a count set signal and increasing bits by a count increase signal and a carry to output an internal address signal and a final state signal;
- and a plurality of logical combining means, each for combining the carry and the final state signal of each unit counter to apply the combined signal to the carry of a next unit counter, the unit counter including:
- a first NAND gate for NAND-operating the count increase signal and the carry to output an inverted increase control signal;
- a first inverter for inverting the output of the first NAND gate to output an increase control signal;
- a multiplicity of counting means, each receiving the bit combinations of the unit external address signal to output a number of state signals;
- a multiplicity of state means for presetting all possible bit combinations of the unit external address signal and selectively outputting bit combinations as a plurality of internal address signals in response to the state signals outputted from the multiplicity of counting means;
- and
- a second to a fifth inverter, an input of the second inverter coupled to an output of the third inverter and an input of the third inverter coupled to an output of the second inverter, an input of the fourth inverter coupled to an output of the fifth inverter and an input of the fifth inverter coupled to an output of the fourth inverter, for latching the plurality of the internal address signals selectively outputted by the multiplicity of the state means.
A multi-bit counter comprising a multiplicity of unit counters, each for receiving bit combinations of a unit external address signal, setting an external input by a count set signal and increasing bits by a count increase signal and a carry to output an internal address signal and a final state signal;
- and a plurality of logical combining means, each for combining the carry and the final state signal of each unit counter to apply the combined signal to the carry of a next unit counter, the unit counter including:
- set controlling means receiving a plurality of propagating signals and a count set signal to output a multiplicity of set signals;
- increasing controlling means receiving a carry of a previous stage and a count increase signal to output a number of increase control signal;
- a multiplicity of counting means, each receiving the bit combinations of the unit external address signal to output a number of state signals;
- a multiplicity of state means for presetting all possible bit combinations of the unit external address signal and selectively outputting bit combinations as a plurality of internal address signals in response to the state signals outputted from the multiplicity of counting means;
- and
- a second to a fifth inverter, an input of the second inverter coupled to an output of the third inverter and an input of the third inverter coupled to an output of the second inverter, an input of the fourth inverter coupled to an output of the fifth inverter and an input of the fifth inverter coupled to an output of the fourth inverter, for latching the plurality of the internal address signals selectively outputted by the multiplicity of the state means.
A multi-bit counter having a plurality of counter units, the multi-bit counter comprising:
- a first counter unit having a first input for receiving a first external address signal, a second input for receiving a second external address signal, a third input for receiving a count set signal, a fourth input for receiving a count increase signal and a fifth input for receiving a carry signal, a first output for providing a first internal address signal, a second output for providing a second internal address signal and a third output for providing a first final state signal;
- a carry generator circuit having a first input for receiving the first final state signal of the first unit counter, a second input coupled to the fifth input of the first counter unit, an output for providing a combined carry signal;
- and
- a second counter unit having a first input for receiving a third external address signal, a second input for receiving a fourth external address signal, a third input for receiving the count set signal, a fourth input for receiving the count increase signal, a fifth input for receiving the combined carry signal from the carry generator circuit, a first output for providing a third internal address signal, a second output for a fourth internal address signal and a third output for providing a second final state signal.
A counter circuit comprising:
- a first logic circuit for receiving a count increase signal and a carry signal to output an increase control signal and an inverted increase control signal;
- a state control unit for receiving a count set signal, a first external address signal and a second address signal to output a state signal and an inverted state signal, wherein the count set signal, the increase control signal and the inverted increase control signal are configured to selectively output the state signal and the inverted state signal;
- and
- a state unit for presetting all possible bit combinations of the first external address signal and the second external address signal to selectively output bit combinations of a first internal address signal and a second internal address signal, wherein the state signal and the inverted state signal are configured to selectively output said bit combinations of the internal address signals.
A multi-bit counter comprising a multiplicity of unit counters, each for receiving bit combinations of a unit external address signal, setting an external input by a count set signal and increasing bits by a count increase signal and a carry to output an internal address signal and a final state signal, and a plurality of logical circuits, each for combining the carry and the final state signal of each unit counter to apply the combined signal to a carry of a next unit counter, the unit counter including:
- a logic gate for receiving the count increase signal and the carry to output an inverted increase control signal;
- a first inverter for inverting the output of the logic gate to output an increase control signal;
- a plurality of state control units, each receiving the bit combinations of the unit external address signal to output a number of state signals;
- a plurality of state units for presetting all possible bit combinations of the unit external address signal and selectively outputting bit combinations as a plurality of internal address signals in response to the state signals outputted from the plurality of state control units;
- and
- a second to a fifth inverter, an input of the second inverter coupled to an output of the third inverter and an input of the third inverter coupled to an output of the second inverter, an input of the fourth inverter coupled to an output of the fifth inverter and an input of the fifth inverter coupled to an output of the fourth inverter, for latching the plurality of the internal address signals selectively outputted by the plurality of the state units.
A multi-bit counter comprising a plurality of unit counters, each for receiving bit combinations of a unit external address signal, setting an external input by a count set signal and increasing bits by a count increase signal and a carry to output an internal address signal and a final state signal, and a plurality of logical circuits, each for combining the carry and the final state signal of each unit counter to apply the combined signal to a carry of a next unit counter, the unit counter including:
- a set controlling unit receiving a plurality of propagating signals and a count set signal to output a multiplicity of set signals;
- an increase control unit receiving a carry of a previous stage and a count increase signal to output an increase control signal;
- a plurality of state control units, each receiving the bit combinations of the unit external address signal to output a number of state signals;
- a plurality of state units for presetting all possible bit combinations of the unit external address signal and selectively outputting bit combinations as a plurality of internal address signals in response to the state signals outputted from the plurality of state control units;
- and
- a second to a fifth inverter, an input of the second inverter coupled to an output of the third inverter and an input of the third inverter coupled to an output of the second inverter, an input of the fourth inverter coupled to an output of the fifth inverter and an input of the fifth inverter coupled to an output of the fourth inverter, for latching the plurality of the internal address signals selectively outputted by the multiplicity of the state units.
A counter circuit comprising:
- a first logic circuit for receiving at least one propagating signal and a count set signal to output a one or more set signals;
- a second logic circuit for receiving a carry signal and a count increase signal to output an increase control signal;
- a state control unit for receiving a first external address signal and a second external address signal to output a state signal and an inverted state signal, wherein the set signal, the increase control signal and the inverted increase control signal are configured to selectively output the state signal and the inverted state signal;
- and
- a state unit for presetting all possible bit combinations of the first external address signal and the second external address signal to selectively output bit combinations of a first internal address signal and a second internal address signal, wherein the state signal and the inverted state signal are configured to selectively output said bit combinations of the internal address signals.
Dependencies are inferred from the claim text.