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US 6,556,644 B2Granted
Frequency multiplier circuit and method using above circuit for a period time division in subperiods, for a brushless motor
AssigneeSTMicroelectronics S.r.l.
InventorRoberto Bardelli
Life of this patent
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Abstract
A frequency multiplier circuit and a controlling method thereof, which measures a period of a waveform by counting cycles of a fixed frequency timing signal, and reproduces the period by adding a number of prefixed length subperiods of the fixed frequency to the cycle count, making it as equal as possible to the period, so to minimize the reproduction error.
Claims16
A frequency multiplier circuit comprising:
- a first input terminal arranged to receive a periodic signal having a period;
- a first counter circuit, implemented to execute counting at a fixed first frequency proportional to a timing frequency that is greater than the inverse of said period, said first counter circuit determining a first count value that includes a count vector of N most significant bits and a vector ADJ of i least significant bits;
- a register coupled to said first counter circuit to receive said first count value;
- a second counter circuit implemented to execute counting at said timing frequency;
- and
- an adder configured to increase by vector ADJ every 2i subperiods of said period.
3 more elements
A method to generate a period time division signal in subperiods, comprising:
- receiving a periodic signal having a period;
- accepting a timing frequency greater than the inverse of said period;
- executing a counting by a first counter at a first fixed frequency proportional to said timing frequency, the counting including a count vector of N most significant bits and a reproduction error vector ADJ of i least significant bits;
- storing a value of said counting in a register;
- executing a counting by a second counter circuit at said timing frequency;
- adding, to the counting in said register, ADJ subdivisions every 2i subdivisions of said period;
- comparing an output value of said register and an output value of said second counter;
- and
- generating a second frequency such as to minimize the reproduction error.
6 more elements
A device comprising:
- an input terminal configured to receive a repeating periodic signal having a period;
- a first counter counting at a first frequency A wherein the first frequency is approximately equal to a desired multiple M of the reciprocal of the period, and having a reset terminal coupled to the input terminal such that the periodic signal resets the first counter;
- a second counter counting at a second frequency B wherein the second frequency is a multiple of the first frequency, and wherein the relationship of the second frequency B to the first frequency A may be expressed as B=A*2i, where 2i is the multiple, the second counter having a reset terminal coupled to the input terminal such that the periodic signal resets the second counter;
- a register having an input coupled to an output of the second counter and configured to store i least significant bits of the second counter as an integer ADJ, the register having a reset terminal coupled to the input terminal such that the register stores a new value ADJ at each periodic signal;
- and
- a circuit configured to adjust the first frequency by a value equal to ADJ cycles of the second frequency every M cycles of the first frequency.
3 more elements
A method comprising:
- receiving a repeating periodic signal at a guide frequency;
- counting at a first frequency approximately equal to a desired multiple M of the guide frequency, the counting restarting at each periodic signal;
- counting at a second frequency equal to a multiple 2i of the first frequency, the counting restarting at each periodic signal;
- storing a number i of least significant bits of the counting at the second frequency as an integer ADJ;
- adjusting the first frequency by a value equal to ADJ cycles of the second frequency every M cycles of the first frequency.
2 more elements
Dependencies are inferred from the claim text.