Majority filter counter circuit

A filter counter circuit for use with a delay locked loop circuit, the filter counter circuit comprising:

• a counter for counting to a predetermined number before causing a delay of an output signal of a delay locked loop circuit, wherein when a phase detector of said delay locked loop circuit transmits a first shift signal indicating a shift left, said counter increments for each subsequent shift left signal transmitted by said phase detector and decrements for each shift right signal transmitted by said phase detector, and wherein when said phase detector transmits a first shift signal indicating a shift right, said counter increments for each subsequent shift right signal transmitted by said phase detector and decrements for each shift left signal transmitted by said phase detector;
• an increment signal generator coupled to an input of said counter for generating an increment signal instructing said counter to increment and to decrement in response to said phase detector transmitting said shift right and shift left signals, depending upon which of said shift right and shift left signals is said first shift signal;
• a shift signal generator, an input of which is coupled to an output of said phase detector and an output of which is coupled to an input of said increment signal generator, said shift signal generator configured to generate a shift right (SR) signal when said phase detector transmits a shift right signal, said shift generator also being configured to generate a shift left (SL) signal when said phase detector transmits a shift left signal, wherein when said SR signal causes said increment signal generator to generate an increment signal, said SL signal causes said increment signal generator to generate a decrement signal, and vice versa;
• a first shift recorder, at least a first input of which is coupled to an output of said counter for receiving said predetermined number, at least a second input of which is coupled to an output of said shift signal generator for receiving said SR and SL signals, said first shift recorder recording whether a first shift received from said shift signal generator is a SR or a SL, wherein whichever signal is received first, each subsequent receipt of said first received signal causes an increment of said counter;
• and
• a counter resetter, at least a first input of which is coupled to said counter for receiving said predetermined number, at least a second input of which is coupled to said first shift recorder for receiving said recorded first shift signal, at least a first output of said counter resetter being coupled to a shift register of said delay locked loop circuit, said counter resetter resets said counter upon said counter reaching said predetermined number, said counter resetter also respectively transmits a right-shift pulse and a left-shift pulse to said shift register when said recorded first shift signal is a SR and a SL signal.

A delay locked loop circuit, comprising:

• an adjustable delay line for receiving an applied signal and providing a delayed output signal;
• a phase detector for comparing a signal representing said output signal with a reference signal representing said applied signal and providing shift left or shift right signals;
• a counter circuit for counting from a first value to a second value, said counting circuit being responsive to an output of said phase detector and determining if a first output signal received from said phase detector after said counter is reset is a shift left or shift right signal, said counter circuit counting to said second value for each subsequently received shift left or shift right signal which is the same as said first received output signal and counting towards said first value for each subsequently received shift left or shift right signal which is not the same as said first received output signal, said counter providing a shift left or shift right output when said second count value is achieved and in accordance with whether said first received output signal was a shift left or shift right signal;
• and
• an adjustment circuit for adjusting said delay line with a shift right or shift left instruction in accordance with the shift left or shift right output of said counter circuit.

A method for delaying shifting of an output of a delay locked loop circuit, the method comprising:

• incrementing a counter to a predetermined number, wherein when said counter is at an initial value and a phase detector of said delay locked loop circuit transmits a shift signal indicating a shift left, said counter increments for each subsequent shift left signal transmitted by said phase detector and decrements for each shift right signal transmitted by said phase detector, and wherein when said counter is at said initial value and said phase detector transmits a shift signal indicating a shift right, said counter increments for each subsequent shift right signal transmitted by said phase detector and decrements for each shift left signal transmitted by said phase detector;
• when said counter has incremented to said predetermined number, shifting said output signal of said delay locked loop circuit by transmitting a left shift signal to a shift register of said delay locked loop circuit if said phase detector transmitted a signal indicating a shift left when said counter was at said initial value, and transmitting a right shift signal to said shift register if said phase detector transmitted a signal indicating a shift right when said counter was at said initial value;
• generating an increment signal instructing said counter to increment and to decrement;
• transmitting said increment signal to said counter in response to said phase detector transmitting said shift right and shift left signals;
• resetting said counter to said initial value;
• recording a new shift signal transmitted by said phase detector when said counter is at said initial value, said newly recorded shift signal being one of a shift left signal and a shift right signal, wherein each subsequent transmission by said phase detector of said newly recorded shift signal causes said counter to increment;
• generating a no shift (NS) signal in response to said phase detector transmitting neither a shift right signal nor a shift left signal;
• generating a decrement signal and transmitting said decrement signal to said counter;
• and
• decrementing said counter in response to receiving said decrement signal.

A method for delaying shifting of an output of a delay locked loop circuit, the method comprising:

• comparing, with a phase detector, a signal representing an output signal of said delay locked loop circuit with a reference signal representing an applied signal and providing shift left or shift right signals;
• counting, with a counter circuit, from a first value to a second value and determining if a first output signal received from said phase detector after said counter is reset is a shift left or shift right signal, said counter circuit counting to said second value for each subsequently received shift left or shift right signal which is the same as said first detected output signal and counting towards said first value for each subsequently received shift left or shift right signal which is not the same as said first detected output signal;
• providing a shift left or shift right output from said counter when said second count value is achieved and in accordance with whether said first output signal was a shift left or shift right signal;
• and
• adjusting said delay line with a shift right or shift left instruction in accordance with the output of said counter circuit.

A processor system, comprising:

• a processor;
• a semiconductor memory circuit coupled to said processor, at least one of said semiconductor memory circuit and said processor having a filter counter circuit for use with a delay locked loop circuit, the filter counter circuit comprising:
• a counter for counting to a predetermined number before causing a delay of an output signal of said delay locked loop circuit, wherein when a phase detector of said delay locked loop circuit transmits a first shift signal indicating a shift left, said counter increments for each subsequent shift left signal transmitted by said phase detector and decrements for each shift right signal transmitted by said phase detector, and wherein when said phase detector transmits a first shift signal indicating a shift right, said counter increments for each subsequent shift right signal transmitted by said phase detector and decrements for each shift left signal transmitted by said phase detector;
• an increment signal generator coupled to an input of said counter for generating an increment signal instructing said counter to increment and to decrement in response to said phase detector transmitting said shift right and shift left signals, depending upon which of said shift right and shift left signals is said first shift signal;
• a shift signal generator, an input of which is coupled to an output of said phase detector and an output of which is coupled to an input of said increment signal generator, said shift signal generator configured to generate a shift right (SR) signal when said phase detector transmits a shift right signal, said shift signal generator also being configured to generate a shift left (SL) signal when said phase detector transmits a shift left signal, wherein when said SR signal causes said increment signal generator to generate an increment signal, said SL signal causes said increment signal generator to generate a decrement signal, and vice versa;
• a first shift recorder, at least a first input of which is coupled to an output of said counter for receiving said predetermined number, at least a second input of which is coupled to an output of said shift signal generator for receiving said SR and SL signals, said first shift recorder recording whether a first shift signal received from said shift signal generator is a SR or a SL, wherein whichever signal is received first, each subsequent receipt of said first received signal causes an increment of said counter;
• a counter resetter, at least a first input of which is coupled to said counter for receiving said predetermined number, at least a second input of which is coupled to said first shift recorder for receiving said recorded first shift signal, at least a first output of said counter resetter being coupled to a shift register of said delay locked loop circuit, said counter resetter resets said counter upon said counter reaching said predetermined number, said counter resetter also respectively transmits a right-shift pulse and a left-shift pulse to said shift register when said recorded first shift signal is a SR and a SL signal.

A processor system, comprising:

• a processor;
• a semiconductor memory circuit coupled to said processor, at least one of said semiconductor memory circuit and said processor having a delay locked loop circuit, the delay locked loop circuit comprising:
• an adjustable delay line for receiving an applied signal and providing a delayed output signal;
• a phase detector for comparing a signal representing said output signal with a reference signal representing said applied signal and providing shift left or shift right signals;
• a counter circuit for counting from a first value to a second value, said counting circuit being responsive to an output of said phase detector and determining if a first output signal received from said phase detector after said counter is reset is a shift left or shift right signal, said counter circuit counting to said second value for each subsequently received shift left or shift right signal which is the same as said first received output signal and counting towards said first value for each subsequently received shift left or shift right signal which is not the same as said first received output signal, said counter providing a shift left or shift right output when said second count value is achieved and in accordance with whether said first received output signal was a shift left or shift right signal;
• and
• an adjustment circuit for adjusting said delay line with a shift right or shift left instruction in accordance with the shift right or shift left output of said counter circuit.