US 6,556,640 B1Granted

Digital PLL circuit and signal regeneration method

AssigneeNEC Corporation

InventorMitsuo Baba

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Abstract

An input data signal is digitally sampled by a data sampling section using an N-phase clock signal including N clock signals whose frequencies are almost the same as the bit rate of the input data signal and whose phases has been successively shifted by 1/N of the clock cycle, and thereby a parallel sample data signal including N sample data signals is obtained. An edge point detection operation section detects edge points in the N sample data signals in one cycle of an extracted clock signal and outputs an edge point operation output signal. A clock signal extraction section selects a clock signal from the N-phase clock signal based on the information of the edge point operation output signal and outputs the selected clock signal as the extracted clock signal. A delay section delays the N sample data signals of the parallel sample data signal and thereby outputs a parallel delayed sample data signal including N delayed sample data signals. A data regeneration section selects a delayed sample data signal from the N delayed sample data signals based on the information of the edge point operation output signal and outputs the selected delayed sample data signal as a regenerated data signal. Due to the delay by the delay section, extraction time of the digital PLL circuit can be decreased to 0 without enlarging the overhead in the input data signal.

Claims32

Dependent claims

A digital PLL circuit comprising:

a data sampling means which is supplied with an input data signal and an N-phase clock signal (N:
integer larger than 1) including N clock signals whose frequencies are almost the same as the bit rate of the input data signal and whose phases has been successively shifted by 1/N of the clock cycle, for digitally sampling the input data signal using the N clock signals and thereby outputting a parallel sample data signal including N sample data signals;
an edge point detection operation means for acquiring the N sample data signals of the parallel sample data signal, detecting edge points in the acquired N sample data signals in one cycle of an extracted clock signal, and outputting an edge point operation output signal which includes information on the edge points in one cycle of the extracted clock signal;
a clock signal extraction means which is supplied with the N-phase clock signal and the edge point operation output signal outputted by the edge point detection operation means, for selecting a clock signal from the N clock signals of the N-phase clock signal based on the information of the edge point operation output signal and outputting the selected clock signal as the extracted clock signal;
a delay means for delaying the N sample data signals of the parallel sample data signal supplied from the data sampling means and thereby outputting a parallel delayed sample data signal including N delayed sample data signals;
and
a data regeneration means which is supplied with the parallel delayed sample data signal outputted by the delay means and the edge point operation output signal outputted by the edge point detection operation means, for selecting a delayed sample data signal from the N delayed sample data signals of the parallel delayed sample data signal based on the information of the edge point operation output signal and outputting the selected delayed sample data signal as a regenerated data signal.

4 more elements

A signal regeneration method comprising the steps of:

a data sampling step in which an input data signal is digitally sampled using an N-phase clock signal (N:
integer larger than 1) including N clock signals whose frequencies are almost the same as the bit rate of the input data signal and whose phases has been successively shifted by 1/N of the clock cycle, and thereby a parallel sample data signal including N sample data signals is obtained;
an edge point detection operation step in which the N sample data signals of the parallel sample data signal are acquired, edge points in the acquired N sample data signals in one cycle of an extracted clock signal are detected, and an edge point operation output signal which includes information on the edge points in one cycle of the extracted clock signal is generated;
a clock signal extraction step in which the extracted clock signal is selected from the N clock signals of the N-phase clock signal based on the information of the edge point operation output signal;
a delay step in which the N sample data signals of the parallel sample data signal are delayed and thereby a parallel delayed sample data signal including N delayed sample data signals are obtained;
and
a data regeneration step in which a delayed sample data signal is selected from the N delayed sample data signals of the parallel delayed sample data signal based on the information of the edge point operation output signal and the selected delayed sample data signal is outputted as a regenerated data signal.

4 more elements

Dependencies are inferred from the claim text.