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US 6,556,638 B1Granted
Method and apparatus for providing increased data speed using synchronization and bit robbing techniques
AssigneeGoDigital Networks Corporation
InventorThomas L. Blackburn
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Abstract
Method and apparatus for transmitting encoded signals with increased data speed in communications system using system clock synchronization and bit robbing techniques to attain high transmission rates is provided.
Claims21
A communication system, comprising:
- a codec interface for encoding an analog signal to generate an encoded digital signal;
- a clock configured to receive a network clock signal from a central office switch and to generate a master clock signal, wherein the master clock signal is synchronized to the network clock signal;
- and
- a framer coupled to the codec interface for receiving the encoded digital signal, and coupled to the clock for receiving the synchronized master clock signal, wherein the framer further includes:
- a first register for storing the encoded digital signal;
- a second register for storing signaling information;
- a transmit buffer for temporarily storing a first portion of the encoded digital signal;
- an overhead buffer for temporarily storing either a second portion of the encoded digital signal or the signaling information;
- and
- a framer clock for synchronizing the first and second registers, the transmit buffer and the overhead buffer to the synchronized master clock signal;
- wherein when there is no signaling information change in the second register, the first portion of the encoded digital signal is multiplexed with the second portion of the encoded digital signal, and further, when there is signaling information change in the second register, the first portion of the encoded digital signal is multiplexed with the signaling information.
8 more elements
A method of providing a communication system, comprising the steps of:
- encoding an analog signal and generating an encoded digital signal;
- receiving a network clock signal and generating a master clock signal, wherein the master clock signal is synchronized to the network clock signal;
- latching the encoded digital signal in a first register;
- latching signaling information in a second register;
- temporarily storing a first portion of the encoded digital signal in a first buffer;
- temporarily storing either a second portion of the encoded digital signal or the signaling information in a second buffer;
- synchronizing the first and second registers and the first and second buffers with the synchronized master clock signal;
- wherein when there is no signaling information change in the second register, multiplexing the first portion of the encoded digital signal with the second portion of the encoded digital signal, and further, when there is signaling information change in the second register, multiplexing the first portion of the encoded digital signal with the signaling information.
5 more elements
Dependencies are inferred from the claim text.