Semiconductor device having decision feedback equalizer

A signal processing system comprising:

• an amplifier for amplifying an input signal in accordance with a predetermined gain and generating an amplified input signal;
• an A/D converter, connected to the amplifier, for sampling the amplified input signal in accordance with the clock signal and generating a sampled data;
• a decision feedback equalizer, connected to the A/D converter, for generating a decoded signal by eliminating intersymbol interference from the sampled data, the decision feedback equalizer including,
• a feed forward filter for filtering the sampled data to generate filtered data,
• an adder, connected to the feed forward filter, for adding the filtered data and a feedback signal to generate an equalization signal,
• a decision unit, connected to the adder, for comparing the equalization signal with a predetermined reference signal to generate a decision signal,
• a shift register, connected to the decision unit, for storing the decision signal, and
• a feedback filter, connected to the shift register and the adder, for receiving the decision signal stored in the shift register and generating the feedback signal;
• a replica signal generator, connected to the shift register, for supplying a replica signal corresponding to a predetermined decision result to the shift register in place of the decision signal at a time of phase and frequency matching;
• a timing recovery circuit, connected to the A/D converter, the adder and the shift register, for generating the clock signal using the equalization signal and the decision signal and supplying the clock signal to the A/D converter, wherein the timing recovery circuit matches a phase and frequency of the clock signal with a phase and frequency of the input signal using the equalization signal and the decision signal and wherein at a time of phase and frequency matching, the timing recovery circuit generates the clock signal using the equalization signal and the replica signal;
• and
• a gain control circuit, connected to the amplifier, the adder and the shift register, for generating a control signal for controlling the predetermined gain of the amplifier using the equalization signal and the decision signal, wherein at the time of phase and frequency matching, the gain control circuit generates the control signal using the equalization signal and the replica signal.

A semiconductor device comprising:

• a decision feedback equalizer for generating a decision signal from sampled data generated by sampling an input signal in accordance with a clock signal;
• a replica signal generator, connected to the decision feedback equalizer, for generating a replica signal corresponding to a predetermined decision result at a time when a phase and frequency of the clock signal matches with a phase and frequency of the input signal;
• and
• a selector, connected to the replica signal generator, for selecting one of the decision signal and the replica signal.

A semiconductor device comprising:

• a decision feedback equalizer for generating a decoded signal by eliminating intersymbol interface from sampled data generated by sampling an input signal in accordance with a clock signal, the decision feedback equalizer including,
• a feed forward filter for filtering the sampled data to generate filtered data,
• an adder, connected to the feed forward filter, for adding the filtered data and a feedback signal to generate an equalization signal,
• a decision unit, connected to the adder, for comparing the equalization signal with a predetermined reference signal to generate a decision signal,
• a shift register, connected to to the decision unit, for storing the decision signal, and
• a feedback filter;
• connected to the shift register and the adder, for receiving the decision signal stored in the shift register and generating the feedback, wherein the semiconductor device matches a phase and frequency of the clock signal with a phase and frequency of the input signal using the equalization signal and the decision signal;
• and
• a replica signal generator, connected to the shift register, for supplying a replica signal corresponding to a predetermined decision result of the shift register in place of the decision signal at a time of phase and frequency matching.

A method for executing a waveform equalization, comprising:

• sampling an input signal in accordance with a clock signal to generate sampled data;
• generating a decision signal from the sampled data;
• generating a feedback signal on the basis of the decision signal;
• generating an equalization signal on the basis of the feedback signal;
• and
• generating a replica signal corresponding to a predetermined decision result at a time when a phase and frequency of the clock signal matches with a phase and frequency of the imput signal.

A method for controlling a decision feedback equalizer, comprising:

• sampling an input signal in accordance with a clock signal to generate sampled data;
• generating a decision signal from the sampled data;
• generating a replica signal corresponding to a predetermined decision result at a time when a phase and frequency of the clock signal matches with a phase and frequency of the input signal;
• and
• selecting one of the decision signal and the replica signal to generate an equalization signal.