Digital cross connect and add/drop multiplexing device for SDH or SONET signals

Interconnection apparatus for high-speed signals organized in synchronous frames, said high-speed signals including a plurality of low-speed data signals as tributary signals, said interconnection apparatus comprising:

• a plurality of parallel processing modules (9-T, 9-R;
• 66-1, . . . 66-4) with first interfaces (5, 6;
• 12-1 . . . 12-4;
• 12-i-T, 12-i-R) and second interfaces (7,8;
• 16-1 . . . 16-4;
• 16-i-T, 16-i-R), each of said plurality of parallel processing modules provided for manipulating portions of said tributary signals in parallel with the manipulating of other portions of said tributary signals by other of said plurality of parallel processing modules, and
• configurable multiplexing/demultiplexing means (14, 34, 38, 40, 42) enabling each said plurality of parallel processing module (66-i) to access any portion of an arbitrarily preselected tributary signal in said high-speed signals and providing said accessed portion to at least one of said plurality of parallel processing modules without disassembling and demultiplexing said signals;
• wherein predetermined fixed connections (76) are provided among the second interfaces (16-i) of the parallel processing modules (9-T, 9-R;
• 66-i), whereby, based on this fixed interconnection scheme and the operation of the configurable multiplexing/demultiplexing means (14;
• 24-i, 28-i;
• 34, 38, 40, 42), any tributary signals can be arbitrarily rearranged between synchronous frames arriving on incoming lines (20) and synchronous frames departing on outgoing lines (26).

Interconnection apparatus for high-speed signals organized in synchronous frames, said high-speed signals including a plurality of low-speed data signals as tributary signals, said interconnection apparatus comprising:

• a plurality of parallel processing modules (9-T, 9-R;
• 66-1, . . . 66-4) with first interfaces (5,6;
• 12-1 . . . 12-4;
• 12-i-T, 12-i-R) and second interfaces (7,8;
• 16-1 . . . 16-4;
• 16-i-T, 16-i-R), each of said plurality of parallel processing modules provided for manipulating portions of said tributary signals in parallel with the manipulating of other portions of said tributary signals by other of said plurality of parallel processing modules, and
• configurable multiplexing/demultiplexing means (14, 34, 38, 40, 42) enabling each said plurality of processing module (66-i) to access any portion of an arbitrarily preselected tributary signal in said high-speed signals and providing said accessed portion to at least one of said plurality of parallel processing modules without disassembling and demultiplexing said signals;
• wherein predetermined fixed connections (76) are provided among the second interfaces (16-i) of the parallel processing modules (9-T, 9-R;
• 66-i) and also between the second interfaces of said modules and local ports (78-1 . . . 78-4), whereby, based on this fixed interconnection scheme and the operation of said configurable multiplexing/demultiplexing means (14;
• 34, 38, 40, 42), tributary signals can be arbitrarily rearranged between synchronous frames arriving on incoming lines (20) and synchronous frames departing on outgoing lines (26) and can be arbitrarily exchanged between local ports and arriving or departing synchronous frames.

A method for providing interconnection processing of high speed signals organized in synchronous frames, said high speed signals including a plurality of low-speed data signals as tributary signals, comprising the steps of:

• selectively accessing portions of said high speed signals at configurable multiplexing/demultiplexing means without demultiplexing or disassembling said signals;
• providing the selectively accessed portions of said high speed signals for parallel processing at a plurality of parallel processing modules having first interfaces and second interfaces;
• and
• providing a pipeline arrangement at said multiplexing/demultiplexing means for sequentially transferring a high-speed signal along the plurality of parallel processing modules and for selectively transferring tributary signals into and out of the first interfaces of said plurality of parallel processing modules, according to configuration information provided to control means for said multiplexing/demultiplexing means.

A program storage device readable by machine tangibly embodying a program of instructions executable by the machine to perform method steps for providing interconnection processing of high speed signals organized in synchronous frames, said high speed signals including a plurality of low-speed data signals as tributary signals, said method comprising the steps of:

• selectively accessing portions of said high speed signals at configurable multiplexing/demultiplexing means without demultiplexing or disassembling said signals;
• providing the selectively accessed portions of said high speed signals for parallel processing at a plurality of parallel processing modules having first interfaces and second interfaces;
• and
• providing a pipeline arrangement at said multiplexing/demultiplexing means for sequentially transferring a high-speed signal along the plurality of parallel processing modules and for selectively transferring tributary signals into and out of the first interfaces of said plurality of parallel processing modules, according to configuration information provided to control means for said multiplexing/demultiplexing means.

A method for providing interconnection processing of high speed signals, said high speed signals including a plurality of low-speed data signals as tributary signals and being organized in synchronous frames, comprising the steps of:

• selectively accessing portions of said high speed signals at configurable multiplexing/demultiplexing means without demultiplexing or disassembling said signals;
• providing the selectively accessed portions of said high speed signals for parallel processing at a plurality of parallel processing modules having first interfaces and second interfaces;
• and
• providing predetermined fixed connections among the second interfaces of the plurality of parallel processing modules, whereby, based on this fixed interconnection scheme and the operation of the configurable multiplexing/demultiplexing means, any tributary signals can be arbitrarily rearranged between synchronous frames arriving on incoming lines and synchronous frames departing on outgoing lines.

A method for providing interconnection processing of high speed signals, said high speed signals including a plurality of low-speed data signals as tributary signals and being organized in synchronous frames, comprising the steps of:

• selectively accessing portions of said high speed signals at configurable multiplexing/demultiplexing means without demultiplexing or disassembling said signals;
• providing the selectively accessed portions of said high speed signals for parallel processing at a plurality of parallel processing modules having first interfaces and second interfaces;
• and
• providing predetermined fixed connections among the second interfaces of the plurality of parallel processing modules and also between the second interfaces of the plurality of parallel processing modules and local ports, whereby, based on this fixed interconnection scheme and the operation of the configurable multiplexing/demultiplexing means, tributary signals can be arbitrarily rearranged between synchronous frames arriving on incoming lines and synchronous frames departing on outgoing lines and can be arbitrarily exchanged between local ports and arriving or departing synchronous frames.

A program storage device readable by machine tangibly embodying a program of instructions executable by the machine to perform method steps for providing interconnection processing of high speed signals, said high speed signals including a plurality of low-speed data signals as tributary signals and being organized in synchronous frames, said method comprising the steps of:

• selectively accessing portions of said high speed signals at configurable multiplexing/demultiplexing means without demultiplexing or disassembling said signals;
• providing the selectively accessed portions of said high speed signals for parallel processing at a plurality of parallel processing modules having first interfaces and second interfaces;
• and
• providing predetermined fixed connections among the second interfaces of the plurality of parallel processing modules, whereby, based on this fixed interconnection scheme and the operation of the configurable multiplexing/demultiplexing means, any tributary signals can be arbitrarily rearranged between synchronous frames arriving on incoming lines and synchronous frames departing on outgoing lines.

A program storage device readable by machine tangibly embodying a program of instructions executable by the machine to perform method steps for providing interconnection processing of high speed signals, said high speed signals including a plurality of low-speed data signals as tributary signals and being organized in synchronous frames, comprising the steps of:

• selectively accessing portions of said high speed signals at configurable multiplexing/demultiplexing means without demultiplexing or disassembling said signals;
• providing the selectively accessed portions of said high speed signals for parallel processing at a plurality of parallel processing modules having first interfaces and second interfaces;
• and
• providing predetermined fixed connections among the second interfaces of the plurality of parallel processing modules and also between the second interfaces of the plurality of parallel processing modules and local ports, whereby, based on this fixed interconnection scheme and the operation of the configurable multiplexing/demultiplexing means, tributary signals can be arbitrarily rearranged between synchronous frames arriving on incoming lines and synchronous frames departing on outgoing lines and can be arbitrarily exchanged between local ports and arriving or departing synchronous frames.