Correction method for clock synchronization with ISDN in cell station for use in private-network-use PHS and a circuit therefor

A correction circuit for clock synchronization with ISDN in cell station for use in private-network-use PHS comprising:

• a permission signal generator circuit for generating a correction permission signal for network synchronization by connection with ISDN;
• a cancellation signal generator circuit for outputting a reset cancellation signal for network synchronization synchronously with a master clock in said system if a clock is extracted from ISDN after it receives the correction permission signal from said permission signal generator circuit;
• a divider circuit for air operating regardless of a connection state with the ISDN for dividing the master clock of said system to output a air side clock, the outputted dividing ratio being changed depending on a phase difference signal to be generated elsewhere;
• a divider circuit for synchronization for dividing said master clock to a predetermined frequency by receiving a reset cancellation signal from said cancellation signal generator circuit, the dividing ratio being changed according to said phase difference signal;
• a network side divider circuit for dividing a clock extracted from the ISDN to said predetermined frequency by receiving a reset cancellation signal from said cancellation signal generator circuit;
• and
• a phase comparator circuit for detecting a phase difference between an outputted clock of said divider circuit for synchronization and an outputted clock of said network side divider circuit when the correction permission signal is outputted from said permission signal generator circuit so as to output said phase difference signal.