Nonvolatile semiconductor memory device and data input/output control method thereof

A flash memory device including memory cell arrays and a memory controller, in which the memory cell array having electrically erasable and programmable memory cells arranged in a matrix of rows and columns, the memory cell array comprising a main field array and a spare field array, further comprising;

• a plurality of latch groups for temporarily storing data to be stored/read in/from the memory cell array, wherein the data comprises normal data bits to be stored in the main field array and additional data bits, associated with the normal data bits, to be stored in the spare field array;
• an address buffer circuit for storing external addresses provided to a first input/output pins;
• a column address register for receiving an address of the external addresses stored in the address buffer circuit as a column address, and for sequentially increasing the column address;
• a selection circuit for sequentially selecting a latch group of the plurality of latch groups in response to the column address outputted from the column address register;
• a data input/output circuit for transferring data sequentially inputted from a second input/output pins to a selected latch group of the plurality of latch groups by being synchronized with a data input signal provided from the memory controller, and for transferring the stored data in the selected latch group to the second input/output pins by being synchronized with a data output signal provided from the memory controller;
• a command register for generating a flag signal indicating column address change in response to a column address change command;
• a short pulse generation circuit for generating a short pulse signal in response to the flag signal;
• an address input period setting circuit for enabling an address input period signal indicating a predetermined address input period in response to the short pulse signal;
• and
• a control logic for controlling the address buffer circuit and the column address register in response to the activation of the address input period signal so that the column address of the external addresses is stored in the column address register.

A flash memory device including memory cell arrays and a memory controller, in which the memory cell arrays having electrically erasable and programmable memory cells arranged in a matrix of rows and columns, the memory cell array comprising a main field array and a spare field array, further comprising:

• a plurality of latch groups for temporarily storing data to be stored/read in/from the arrays, wherein the data comprising normal data bits to be stored in the main field array and additional data bits, associated with the normal data bits, to be stored in the spare field array;
• an address buffer circuit for storing external addresses provided from a first input/output pins;
• a column address register for receiving an address of the external addresses stored signals in the address buffer circuit as a column address, and for sequentially increasing the column address;
• a selection circuit for sequentially selecting a latch group of the plurality of latch groups in response to the column address outputted from the column address register;
• a data input/output circuit for transferring data sequentially inputted from a second input/output pins to a selected latch group of the plurality of latch groups by being synchronized with a data input signal provided from the memory controller, and for transferring the stored data in the selected latch group to the second input/output pins by being synchronized with a data output signal provided from the memory controller;
• a first detection circuit for detecting whether a combination of external control signals CLE, ALE, /WE, and /RE from the memory controller indicates column address change, and generating a flag signal indicating column address change;
• a short pulse generation circuit for generating a short pulse signal in response to the flag signal;
• an address input period setting circuit for enabling an address input period signal indicating a predetermined address input period in response to the short pulse signal;
• and
• a control logic for controlling the address buffer circuit and the column address register in response to the activation of the address input period signal so that the external addresses provided from the first input/output pins are stored in the column address register.

A flash memory device comprising:

• a memory cell array having electrically erasable and programmable memory cells arranged in a matrix of rows and columns, the memory cell array comprising a main field array and a spare field array;
• a plurality of latches for temporarily storing data column to be stored/read in/from the array, the latches being divided into a plurality of latch groups, wherein the data column is composed of normal data bits to be stored in the main field array and additional data bits, associated with the normal data bits, to be stored in the spare field array;
• an address buffer circuit for storing signals provided to input/output pins as an address;
• a column address register for receiving the signals stored in the address buffer circuit as a column address, and for sequentially increasing the received column address;
• a selection circuit for sequentially selecting the latch groups of the plurality of latch groups in response to the column address outputted from the column address register;
• a data input/output circuit for transferring data columns sequentially inputted from the input/output pins to the latches of the selected groups by being synchronized with a data input signal, and for transferring the stored data columns to the input/output pins by being synchronized with a data output signal;
• an address input period setting circuit for generating an address input period signal indicating a predetermined address input period in response to a set signal and a reset signal;
• a control logic for controlling the address buffer circuit and the column address register in response to the address input period signal so that an external address provided to the input/output pins is stored in the column address register;
• and
• a detection circuit for receiving external control signals CLE, ALE, /WE, and /RE, for detecting a start point of the address input period to output the set signal for enabling the address input period signal, and for detecting a finish point of the address input period to output the reset signal for disabling the enabled address input period signal;
• wherein the address buffer circuit stores the external address applied to the input/output pins in response to the address input control signal, and the column address register receives the stored external address in response to the address latch control signal.

A system including a memory controller that receives normal data from a host to internally generate additional data associated with the normal data, and has a buffer memory for temporarily storing the normal data and the additional data;

• and a flash memory device that is coupled to the memory controller, and stores a data comprised of the normal data and the additional data;
• wherein the flash memory device comprises:
• a memory cell array having electrically erasable and programmable memory cells arranged in a matrix of rows and columns, the memory cell array comprising a main field array and a spare field array, wherein the normal data is stored in the main field array and the additional data is stored in the spare field array;
• a plurality of latch groups for temporarily storing the data to be stored in the memory cell array or storing the data read from the array;
• an address buffer circuit for storing external addresses provided from a first the input/output pins;
• a column address register for receiving an address of the external addresses stored in the address buffer circuit as a column address, and for sequentially increasing the column address;
• a selection circuit for sequentially selecting a latch group of the plurality of latch groups in response to the column address outputted from the column address register;
• a data input/output circuit for transferring data sequentially inputted through a second input/output pins to the selected latch group by being synchronized with a data input signal provided from the memory controller, and for transferring the stored data in the selected latch group to the input/output pin by being synchronized with a data output signal provided from the memory controller;
• and
• a controller for controlling the address buffer circuit and the column address register to store the column address of the external addresses in the column address register when the external addresses are applied to the first input/output pins while the data is transferred from the selected latch group to the second input/output pins or vice versa.

A method for controlling data input/output of a nonvolatile semiconductor memory device including a memory cell array having electrically erasable and programmable memory cells arranged in a matrix of rows and columns, the memory cell array comprising a main field array and a spare field array;

• a plurality of latch groups for temporarily storing data to be stored/read in/from the array;
• wherein the data comprises normal data bits to be stored in the main field array and additional data bits, associated with the normal data bits, to be stored in the spare field array;
• an address buffer circuit for storing external addresses provided from a first input/output pins;
• and a column address register for receiving an address of the external addresses stored in the address buffer circuit as a column address, and for sequentially increasing the column address, the method comprising the steps of:
• (a) sequentially selecting a latch group of the plurality of latch groups in response to the column address outputted from the column address register;
• (b) transferring the data from a second input/output pins to the selected latch group by being synchronized with a data input signal provided from the memory controller;
• (c) storing an address of the external addresses in the column address register as a new column address when the external addresses are applied to the memory device while the data is transferred/outputted to/from the selected latch group;
• and
• (d) performing the step of (b) according to the new column address.