Back to results
US 6,556,494 B2Granted
High frequency range four bit prefetch output data path
AssigneeMicron Technology, Inc.
InventorsChristopher K. Morzano, Wen Li
Life of this patent
Estimating the term…
Abstract
A method of transferring a plurality of data bits from memory cells to a data pad via a plurality of output paths. Each of the output paths receives the data bits in parallel and selects one bit among the data bits. Selected bits from each of the output paths is transferred to an output select. A plurality of timing signals are activated in sequence based on alternate phases of two enable signals to serially transfer the data bits from the output select to the data pad.
Claims43
An integrated circuit comprising:
- a plurality of output paths to receive a group of first, second, third and fourth data bits, each of the output paths receives the data bits in parallel;
- an output select connected to the output paths to receive the data bits from the output paths;
- and
- an output stage to receive data bits transferred from the output select to output the data bits to a data pad in a series and within two cycles of a clock signal, wherein the first and the third data bits in the series are output at alternate phases of a first enable signal, wherein the second and fourth data bits in the series are output at alternate phases of a second enable signal, wherein the first and second enable signals are not synchronized.
1 more element
An integrated circuit comprising:
- a plurality of output paths, each of the output paths including:
- a plurality of input nodes to receive a group of bits of data;
- an input select to provide a selected bit selected from the bits of data;
- a first latch connected to the input select to receive the selected bit;
- and
- a second latch connected to the first latch to receive the selected bit from the first latch, wherein the selected bit from each of the output paths is different;
- an output select connected to the output paths to receive the selected bit from each of the output paths;
- and
- an output stage connected to the output select, the output stage serially receiving selected bits from the output select and providing the selected bits to a data pad in two clock cycles.
6 more elements
An integrated circuit comprising:
- a plurality of input nodes to receive a group of M bits of data in parallel;
- a data pad;
- and
- N output paths connected between the input nodes and the data pad, each of the output paths transferring different bits of the group of M bits of data, wherein the group of M bits of data are transferred to the data pad in series by activating a plurality of timing signals, the timing signals being activated at different times by a first and second enable signals, wherein the enable signals are not synchronized, wherein M and N are greater than two.
1 more element
An integrated circuit comprising:
- a plurality of input nodes to receive a group of M bits of data in parallel;
- a data pad;
- and
- N output paths connected between the input nodes and the data pad, each of the output paths transferring different bits of the group of M bits of data, wherein the group of M bits of data are transferred to the data pad in series by activating a plurality of timing signals, the timing signals being activated at different times by a first and second enable signals, wherein the enable signals are not synchronized, wherein M and N are greater than two, wherein one half of the M bits of data is transferred to the data pad in a first clock cycle by activating a first two timing signals, and another half of the M bits of data is transferred to the data pad in a second clock cycle by activating a second two timing signals, wherein M is greater than two.
1 more element
An integrated circuit comprising:
- a plurality of input nodes to receive a group of M bits of data in parallel;
- a data pad;
- and
- N output paths connected between the input nodes and the data pad, each of the output paths transferring different bits of the group of M bits of data, wherein the group of M bits of data are transferred to the data pad in series by activating a plurality of timing signals, the timing signals being activated at different times by a first and second enable signals, wherein the enable signals are not synchronized, wherein M and N are greater than two, wherein one of the first two timing signals is activated following a falling edge of the first enable signal, the other one of the first two timing signals is activated following a rising edge of the second enable signal, and wherein one of the second two timing signal is activated following rising edge of the first enable signal, and the other one of the second two timing signals is activated following falling edge of the second enable signal.
1 more element
A memory device comprising:
- a plurality of memory cells to store a plurality of data bits;
- a plurality of output paths to receive a group of first, second, third and fourth data bits from the memory cells, each of the output paths receives the data bits in parallel;
- an output select connected to the output paths to receive the data bits from the output paths;
- and
- an output stage to receive data bits transferred from the output select to output the data bits to a data pad in a series and within two cycles of a clock signal, wherein the first and the third data bits in the series are output at alternate phases of a first enable signal, wherein the second and the fourth data bits in the series are output at alternate phases of a second enable signal, wherein the first and second enable signals are not synchronized.
2 more elements
A memory device comprising:
- a plurality of memory cells to store a plurality of bits of data;
- a plurality of output paths, each of the output paths including:
- a plurality input nodes to receive a group of bits of data from the memory cells;
- an input select to provide a selected bit selected from the bits of data;
- a first latch connected to the input select to receive the selected bit;
- and
- a second latch connected to the first latch to receive the selected bit from the first latch, wherein the selected bit from each of the output paths is different;
- an output select connected to the output paths to receive the selected bit from each of the output paths;
- and
- an output stage connected to the output select, the output stage serially receiving selected bits from the output select and providing the selected bits to a data pad in two clock cycles.
7 more elements
A memory device comprising:
- a plurality of memory cells to store a plurality of bits of data;
- a plurality of input nodes to receive a group of M bits of data from the memory cells in parallel;
- a data pad;
- and
- N output paths connected between the input nodes and the data pad, each of the output paths transferring different bit of the group of M bits of data, wherein the group of M bits of data are transferred to the data pad in series by activating a plurality of timing signals, the timing signals being activated at different times by a first and second enable signals, wherein the enable signals are not synchronized, wherein M and N are greater than two.
2 more elements
A memory device comprising:
- a plurality of memory cells to store a plurality of bits of data;
- a plurality of input nodes to receive a group of M bits of data from the memory cells in parallel;
- a data pad;
- and
- N output paths connected between the input nodes and the data pad, each of the output paths transferring different bit of the group of M bits of data, wherein the group of M bits of data are transferred to the data pad in series by activating a plurality of timing signals, the timing signals being activated at different times by a first and second enable signals, wherein the enable signals are not synchronized, wherein M and N are greater than two, wherein one half of the M bits of data are transferred to the data pad in a first clock cycle by activating first two timing signals, and another half of the M bits of data are transferred to the data pad in a second clock cycle by activating second two timing signals, wherein M is greater than two.
2 more elements
A system comprising:
- a processor;
- and
- a memory device connected to the processor, the memory device comprising:
- a plurality of memory cells to store a plurality of bits of data;
- a plurality input nodes to receive a group of M bits of data from the memory cells in parallel;
- a data pad;
- and
- N output paths connected between the input nodes and the data pad, each of the output paths transferring different bit of the group of M bits of data, wherein the group of M bits of data are transferred to the data pad in series by activating a plurality of timing signals, the timing signals being activated at different times by a first and second enable signals,
- wherein the enable signals are not synchronized, wherein M and N are greater than two.
6 more elements
A method of operating memory device, the method comprising:
- accessing M bits of data in memory cells, wherein M is greater than two;
- transferring the M bits of data in parallel to an output circuit;
- and
- outputting the M bits of data in series to a data pad from the output circuit within two cycles of a clock signal and based on a first and second enable signals, wherein the first enable signal allows output of even bits of data to the data pad, and the second enable signal allows output of odd bits of data to the data pad.
1 more element
A method of transferring data, the method comprising:
- reading M bits of data in parallel to a plurality of output paths, wherein M is greater than two;
- transferring the M bits of data from the output paths to an output select, wherein each of the output paths transfers different bit of data;
- activating a first and second enable signals;
- activating a plurality of timing signals in series and based on the enable signals;
- transferring the M bits of data in series to an output stage following transitions of the timing signals;
- and
- outputting the M bits of data to a data pad within two cycles of a clock signal.
4 more elements
Dependencies are inferred from the claim text.