Semiconductor storage device and method of testing the same

A semiconductor storage device comprising:

• a plurality of word lines;
• a plurality of pairs of bit lines;
• a plurality of memory cells disposed at intersections of said word lines and said pairs of said bit lines, respectively, each of said memory cells including:
• a capacitor;
• and
• a transistor having a drain coupled to a respective one of said bit lines, a source coupled to said capacitor, and a gate coupled to a respective one of said word lines;
• a plurality of sense amplifiers coupled to said pairs of said bit lines, respectively, each of said sense amplifiers amplifying a voltage between each of said pairs of said bit lines;
• a plurality of bit line pre-charge circuits disposed at said pairs of said bit lines, respectively, each of said bit line pre-charge circuits pre-charging and equalizing the voltage of each of said pairs of the bit lines amplified by each of said sense amplifiers;
• a write amplifier for writing data into said pairs of said bit lines;
• word line deactivating means for deactivating at least one of said word lines in an operation mode other than an ordinary operation mode;
• and
• sense amplifier deactivating means for deactivating at least one of said sense amplifiers in the operation mode other than the ordinary operation mode;
• and
• bit line pair selecting means for selecting at least one of said pairs of said bit lines in the operation mode other than the ordinary operation mode;
• and
• bit line pair potential fixing means for supplying a potential along with a writing operation from said write amplifier in the operation mode other than the ordinary operation mode.

A method of testing a semiconductor storage device, said method comprising the steps of:

• providing said storage device which includes:
• a plurality of word lines;
• a plurality of pairs of bit lines;
• a plurality of memory cells disposed at intersections of said word lines and said pairs of said bit lines, respectively, each of said memory cells including:
• a capacitor;
• and
• a transistor having a drain coupled to one of said bit lines, a source coupled to said capacitor, and a gate coupled to one of said word lines;
• a plurality of sense amplifiers coupled to said pairs of said bit lines, respectively;
• said sense amplifiers amplifying voltages between said pairs of said bit lines, respectively;
• and
• a plurality of bit line pre-charge circuits disposed on said pairs of said bit lines, respectively, said bit line pre-charge circuits pre-charging and equalizing the voltages of said pairs of said bit lines amplified by said sense amplifiers, respectively;
• writing data into said memory cells in an ordinary operation mode;
• applying a potential of opposite data against data written in the memory cells to at least of the pairs of the bit lines in an operation mode, other than the ordinary operation mode, and holding the opposite potential in the pairs of the bit lines;
• and
• reading the data in the ordinary operation mode.

A semiconductor storage device comprising:

• a plurality of word lines;
• a plurality of pairs of bit lines;
• a plurality of memory cells disposed at intersections of said word lines and said pairs of said bit lines, respectively, each of said memory cells including:
• a capacitor;
• and
• a transistor having a drain coupled to one of said bit lines, a source coupled to said capacitor, and a gate coupled to one of said word lines;
• a plurality of memory cell arrays including said memory cells;
• sense amplifiers shared by said memory cell arrays, respectively,
• a plurality of transfer gates for coupling said pairs of said bit lines of memory cell arrays to said sense amplifiers, respectively;
• a plurality of bit line pre-charge circuits disposed in said pairs of said bit lines, respectively, said bit line pre-charge circuits pre-charging and equalizing the voltages of said pairs of said bit lines amplified by said sense amplifiers, respectively;
• word line deactivating means for deactivating at least one of said word lines in an operation mode other than an ordinary operation mode;
• sense amplifier deactivating means for deactivating at least one of said sense amplifiers in the operation mode other than the ordinary operation mode;
• shared gate activating means for activating at least one of said transfer gates in the operation mode other than the ordinary operation mode;
• and
• bit line pair potential fixing means for setting voltages of at least one of said pairs of said bit lines to the same level.

A method of testing a semiconductor storage device, said method comprising the steps of:

• providing said storage device which includes:
• a plurality of word lines;
• a plurality of pairs of bit lines;
• a plurality of memory cells disposed at intersections of the word lines and the pairs of the bit lines, respectively, each of the memory cells including:
• a capacitor;
• and
• a transistor having a drain coupled to one of the bit lines, a source coupled to the capacitor, and a gate coupled to one of the word lines;
• a plurality of memory cell arrays including the memory cells respectively;
• sense amplifiers shared by the memory cell arrays;
• a transfer gate for coupling the pairs of the bit lines of the memory cell arrays to the sense amplifiers;
• and
• a plurality of bit line pre-charge circuits disposed in the pairs of the bit lines, respectively, the bit line pre-charge circuit pre-charging and equalizing the voltages of the pairs of the bit lines amplified by the sense amplifiers, respectively;
• writing data into the memory cells of the semiconductor storage device in an ordinary operation mode;
• applying a potential of opposite data against the data written in the memory cell arrays to the pairs of the bit lines in an operation mode other than the ordinary operation mode, and holding the opposite potential in the pairs of the bit lines;
• and
• reading the data in the ordinary operation mode.