Delay locked loop for use in semiconductor memory device
AssigneeHynix Semiconductor Inc.
InventorJong-Hee Han
Life of this patent
Estimating the term…
Abstract
A delay locked loop is used in a semiconductor memory device. The delay locked loop includes a controllable delay chain block for controlling a delay time of a clock signal coupled thereto, a comparison block for detecting the increase and decrease in the delay time by comparing a reference clock signal with a delayed clock signal generated from the controllable delay chain block, and an instant locking delay control block for controlling the increase and decrease in the delay time of the delay chain block in response to an output signal of the comparison block, the delayed clock signal and the reference clock signal.
Claims18
A delay locked loop for use in a semiconductor memory device, comprising:
- a controllable delay chain means for controlling a delay time of a clock signal coupled thereto;
- a comparison means for comparing a reference clock signal with a delayed clock signal generated from the controllable delay chain means and detecting a need for an increase or decrease of the delay time;
- and
- an instant locking delay control means for detecting whether a locking between the reference clock signal and the delayed clock signal is accomplished,
- wherein, when the locking is accomplished, the instant locking delay control means is operated to compensate for noise detected by the comparison means and to control the controllable delay chain means, and
- wherein, when the locking is not accomplished, the instant locking delay control means is not operated to compensate for noise and the output signals generated by the comparison means are used to directly control the controllable delay chain means.
In a delay locked loop, a delay control circuit for generating a control signal for causing an increase or decrease in a delay time of a delayed clock signal, comprising:
- a time-offset detector coupled to the delayed clock signal and a reference clock signal and configured to generate a first adjustment signal indicating a need for an increase or decrease of the delay time;
- a delay controller coupled to the first adjustment signal and configured to generate a second adjustment signal by applying noise compensation to the first adjustment signal;
- a locking detector coupled to the delayed clock signal and the reference signal and configured to assert a lock signal when a locking condition is satisfied;
- and
- a selector configured to provide one of the first and second adjustment signals as the control signal in response to the lock signal.
In a delay locked loop circuit having a delay chain, a method of providing a delay adjustment signal for controlling a delay time, comprising:
- comparing a delayed clock signal generated by the delayed chain to a reference signal, thereby generating a first adjustment signal;
- applying a noise-compensating condition to the first adjustment signal, thereby generating a second adjustment signal;
- comparing the delayed clock signal and the reference signal, thereby generating a locking signal;
- when the locking signal is in a locked state, selecting the second adjustment signal as the delay adjustment signal;
- and
- when the locking signal is in an unlocked state selecting the first adjustment signal as the delay adjustment signal.
Dependencies are inferred from the claim text.