US 6,556,484 B2 · Plural line buffer type memory LSI

Abstract

In a plural line buffer type memory LSI, a line selection register 16 (holding an address for designating a line buffer) is added. The value of the line selection register 16 is previously updated by a memory access instruction having a room in an address. Thus, it is possible to maintain compatibility with input/output terminals of a general purpose memory LSI, or to prevent the increase in the number of input/output terminals, and also to prevent the increase of the memory access delay attributable to the restriction in connection with the issue of the commands. Accordingly, it is possible to maintain the compatibility with the general purpose memory LSI having no line buffer, or alternatively to prevent the increase of the memory access delay attributable to a restriction in an interval for issuing the commands.

Claims14

Dependent claims

A plural line buffer type memory LSI comprising:

a memory section;
a plural line buffer section including a plurality of line buffers connected to said memory section;
and
a data buffer connected to said plural line buffer section,
so that a data transfer is carried out between said memory section and said plural line buffer section and between said plural line buffer section and said data buffer,
the plural line buffer type memory LSI further comprising a line selection register for designating at least one line buffer in said plural line buffer section.

3 more elements

Dependencies are inferred from the claim text.

Plural line buffer type memory LSI

Life of this patent

Plural line buffer type memory LSI

Life of this patent

Abstract

Claims14