US 6,556,483 B2 · Method and apparatus for synchronous data transfers in a memory device with selectable data or address paths

Abstract

A synchronous dynamic random access memory (“SDRAM”) operates with matching read and write latencies. To prevent data collision at the memory array, the SDRAM includes interim address and interim data registers that temporarily store write addresses and input data until an available interval is located where no read data or read addresses occupy the memory array. During the available interval, data is transferred from the interim data register to a location in the memory array identified by the address in the interim array register. In one embodiment, the SDRAM also includes address and compare logic to prevent reading incorrect data from an address to which the proper data has not yet been written. In another embodiment, a system controller monitors commands and addresses and inserts no operation commands to prevent such collision of data and addresses.

Claims10

Dependent claims

A method of synchronously reading read data from and writing write data to a selected memory array within an integrated memory device, comprising the steps of:

providing a first read command to the memory device during a first interval;
waiting a selected latency period after the first read command has been provided to the memory device;
transferring the read data from the selected memory array to a data bus of the memory device by the end of the latency period in response to the first read command;
providing a write command to the memory device at a second interval immediately following the first read command being applied to the memory device during the first interval and before the end of the latency period;
applying the write data to a data bus the selected latency period after the write command has been provided to the memory device;
and
writing the write data to the selected memory array.

4 more elements

A method of reading read data from and writing write data to a memory device, comprising:

applying a first read command to the memory device;
in response to the first read command, outputting the read data from the memory device a latency period after the first read command has been applied to the memory device;
applying a first write command to the memory device, the first write command being applied to the memory device during the latency period between the time that the first read command is applied to the memory device and the time that the read data responsive to the first read command it output from the memory device;
applying the write data to the memory device, the write data being applied to the memory device the selected latency period after the first write command is applied to the memory device;
and
writing the write data to the memory device responsive to the first write command.

3 more elements

A method of reading read data from and writing write data to a memory device having a memory array, the method comprising:

applying a first read command to the memory device;
applying a first read address to the memory device;
in response to the first read command, outputting the read data from a location in a memory array corresponding to the first read address, the read data being output from the memory device a first latency period after the first read command is applied to the memory device;
applying a first write command to the memory device;
applying a first write address to the memory device;
applying the write data to the memory device, the write data being applied to the memory device the first latency period after the first write command has been applied to the memory device;
and
writing the write data in the memory array responsive to the first write command, the write data being written to a location in the memory array corresponding to the first write address.

5 more elements

Dependencies are inferred from the claim text.

Method and apparatus for synchronous data transfers in a memory device with selectable data or address paths

Life of this patent

Method and apparatus for synchronous data transfers in a memory device with selectable data or address paths

Life of this patent

Abstract

Claims10