Semiconductor memory device
AssigneeNEC Electronics Corporation
InventorsTakato Shimoyama, Hiroyuki Takahashi
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Abstract
According to the disclosed embodiments, a semiconductor memory device may include an address register circuit (406) and data register circuit (411) that can store a write address and write data from one write operation and output the stored write address and write data during a subsequent write operation. In a dynamic random access memory (DRAM) embodiment (400), a precharge and/or refresh operation may follow the writing of previously stored write data. Such an arrangement may reduce and/or eliminate a read after write timing requirement (TWR), which can improve the operating speed of the semiconductor memory device.
Claims20
A semiconductor memory device, comprising:
- a plurality of memory cells that can be selected according to an internal pulse signal that is not generated in response to an external periodic timing signal;
- and
- circuits for storing a write address and write data during one write operation and outputting the stored write address and write data during a subsequent write operation.
A semiconductor memory device, comprising:
- a plurality of SRAM cells arranged into rows, each SRAM cell is a four transistor cell including two driver transistors of a first conductivity type that drive complementary nodes to different potentials and two access transistors of a second conductivity type that couple the complementary nodes to a digit line pair, each row of SRAM cells being selected by a pulse word line signal on a corresponding word line wherein the pulse word line signal is generated in response to an internal pulse signal;
- and
- a pulse generator circuit that generates the internal pulse signal that is not generated in response to an external periodic timing signal.
A semiconductor memory device, comprising:
- a memory cell array of dynamic random access memory (DRAM) cells;
- an address register circuit that can store an address of a previous write operation and output the stored address in response to a subsequent write operation;
- a data register circuit that can store a write data from the previous write operation;
- and
- a write enable signal generator for receiving a write enable signal and generating a row enable signal pulse and column enable signal pulse for writing the write data of the previous write cycle into memory cells corresponding to the write address of the previous cycle.
Dependencies are inferred from the claim text.