3-step write operation nonvolatile semiconductor one-transistor, nor-type flash EEPROM memory cell
AssigneeAplus Flash Technology, Inc.
InventorsFu-Chang Hsu, Hsing-Ya Tsao, Peter W. Lee, Mervyn Wong
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AssigneeAplus Flash Technology, Inc.
InventorsFu-Chang Hsu, Hsing-Ya Tsao, Peter W. Lee, Mervyn Wong
Estimating the term…
In the present invention a three step write of a nonvolatile single transistor cell is disclosed. The three steps comprise erasing, reverse programming and programming which can be applied to a plurality of cell types to produce a symmetrical design and allowing shrinkage of the cell beyond that which is possible with other cells designed to use a two step write procedure. The methodology can be applied to either N-channel or P-channel devices and can be used on various type memory cells such as “ETOX”, “NOR” type, “AND” type, and “OR” type. Erasing and programming steps increase the Vt of the cell transistor, whereas reverse programming decreases the Vt of the cell transistor. Over-erase problems are eliminated using the three step write procedure.
A nonvolatile memory cell contained within an array with a three-step write operation, comprising:
A three step method for programming a flash memory array, comprising:
A single transistor nonvolatile memory cell, comprising:
Dependencies are inferred from the claim text.