Non-volatile memory and semiconductor device

An electrically writable and erasable non-volatile memory comprising a memory cell array in which a plurality of memory cells are arranged in a matrix form and comprising a writing circuit, wherein:

• each of the plurality of memory cells includes a memory element and a selection transistor;
• the memory element includes a charge storage region between an active region and a control gate electrode;
• and
• the writing circuit carries out a writing operation by controlling an amount of current flowing through the memory element and a drain voltage of the memory element.

An electrically writable and erasable non-volatile memory comprising a memory cell array in which a plurality of memory cells are arranged in a matrix form and comprising a writing circuit, wherein:

• each of the plurality of memory cells includes a memory element and a selection transistor;
• the memory element includes a charge storage region between an active region and a control gate electrode;
• the writing circuit has a function to hold an amount of current flowing through the memory element and a drain voltage of the memory element constant;
• and
• the writing circuit carries out a writing operation by controlling a period of time for the amount of the current flowing through the memory element and the drain voltage of the memory element are held constant.

An electrically writable and erasable non-volatile memory comprising a memory cell array in which a plurality of memory cells are arranged in a matrix form and comprising a writing circuit, wherein:

• each of the plurality of memory cells includes a memory element and a selection transistor;
• the memory element includes a charge storage region between an active region and a control gate electrode;
• the memory element stores states of k values not less than two values by an erase state having a threshold voltage Vth0, and states having (k−1) different threshold voltages Vth1, Vth2, . . . , Vth(k−1) higher than the threshold voltage Vth0;
• the writing circuit has a function to hold an amount of current flowing through the memory element and a drain voltage of the memory element constant;
• the writing circuit carries out a writing operation by controlling a writing time in which the amount of the current flowing through the memory element and the drain voltage of the memory element are held constant;
• and
• ratios between writing times tw1, tw2, . . . , tw(k−1) for writing from the erase state to the states having the threshold voltages Vth1, Vth2, . . . , Vth(k−1) are tw1:tw2:
• . . . :tw(k−1)=(Vth1−Vth0):(Vth2−Vth0):
• . . . :(Vth(k−1)−Vth0).