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US 6,556,471 B2Granted
VDD modulated SRAM for highly scaled, high performance cache
AssigneeIntel Corporation
InventorsBarbara A. Chappell, Ian Young
Life of this patent
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Abstract
The present invention provides a device and method for fast SRAM reading and writing. A boost voltage source is provided, wherein the boost voltage source operates to increase a conductance of a latch device in the SRAM cell relative to a conductance of an access device in the SRAM cell. By virtue of the increased relative conductance between the latch and access devices (beta ratio), the access device may be assume a wider width without jeopardizing the read stability of the cell.
Claims15
An SRAM (“Static Random Access Memory”) cell comprising:
- a latch device for storing a state of the SRAM cell;
- an access device for performing a read and write operation;
- a boost voltage source, wherein the boost voltage source is applied to the latch device, the boost voltage increasing a conductance of the latch device relative to a conductance of the access device.
An SRAM (“Static Random Access Memory”) cell comprising:
- a latch device for storing a state of the SRAM cell, the latch device comprising a first inverter and a second inverter, the first inverter and the second inverter configured in a cross-coupled arrangement, wherein each of the first inverter and second inverter includes a respective pull-up device and a pull-down device, the pull-up device operating to pull up a voltage at an output of a respective inverter and the pull-down device operating to pull down a voltage at an output of a respective inverter;
- an access device for performing a read and write operation;
- a boost voltage source, wherein the boost voltage source is applied to the latch device, the boost voltage increasing a conductance of the latch device relative to a conductance of the access device, wherein the boost voltage source is applied to the pull-up devices of the first and second inverters prior to one of a read operation and a write operation.
An SRAM (“Static Random Access Memory”) cell comprising:
- a latch device for storing a state of the SRAM cell, the latch device comprising a first inverter and a second inverter, the first inverter and the second inverter configured in a cross-coupled arrangement, wherein each of the first inverter and second inverter includes a respective pull-up device and a pull-down device, the pull-up device operating to pull up a voltage at an output of a respective inverter and the pull-down device operating to pull down a voltage at an output of a respective inverter;
- an access device for performing a read and write operation, wherein the respective pull-up devices of the inverters are P-MOS transistors fabricated within at least one N well;
- a boost voltage source, wherein the boost voltage source is applied to the latch device, the boost voltage increasing a conductance of the latch device relative to a conductance of the access device, wherein a boost voltage is applied to the N well.
A method for performing fast reading and writing to an SRAM cell including a latch device and an access device comprising:
- providing a boost voltage source, the boost voltage source increasing a conductance of the latch device in the SRAM cell relative to a conductance of the access device in the SRAM cell;
- prior to one of a read operation and a write operation, applying the boost voltage source to a pull-up device in the latch device;
- performing one of a read operation and a write operation on the SRAM cell.
An SRAM array comprising:
- at least one SRAM cell arranged in an array configuration, each SRAM cell comprising:
- a latch device for storing a state of the SRAM cell;
- an access device for performing a read and write operation;
- a plurality of wordlines, each wordline controlling at least one access device;
- a plurality of bitline pairs, wherein each bitline pair is coupled to at least one SRAM cell through an access device;
- a boost voltage source, wherein the boost voltage source is applied to at least one latch device, the boost voltage increasing a conductance of the at least one latch device relative to a conductance of the at least one respective access device.
3 more elements
An SRAM array comprising:
- at least one SRAM cell arranged in an array configuration, each SRAM cell comprising:
- a latch device for storing a state of the SRAM cell;
- an access device for performing a read and write operation;
- a plurality of wordlines, each wordline controlling at least one access device;
- a plurality of bitline pairs, wherein each bitline pair is coupled to at least one SRAM cell through an access device;
- a boost voltage source, wherein the boost voltage source is applied to at least one latch device, the boost voltage increasing a conductance of the at least one latch device relative to a conductance of at least one respective access device, and wherein the boost voltage source is modulated between a first voltage and a boost voltage;
- decoding logic for generating a control signal to control the boost voltage source.
4 more elements
A method for writing to an SRAM cell comprising:
- (a) precharging a bitline pair associated with the cell;
- (b) modulating a voltage applied to a latch device of the cell;
- (c) applying a signal to cause a write operation.
Dependencies are inferred from the claim text.