System and method for multilevel DRAM sensing and restoring

Abstract

A dynamic random access memory for storing one of N levels in each of a plurality of memory cells, the memory cells having storage capacitors coupled to bitline pairs through switches for writing and reading data to and from the memory cells, the memory comprising: at least N−1 bitline pairs, each bitline pair being divided into N−1 sub-bitlines by first switches therebetween; the sub-bitline pairs of each bitline being coupled to adjacent sub-bitline pairs by second switches therebetween, to form N−1 groups of sub-bitlines each for producing one of N−1 reference voltages; sense amplifiers coupled to each sub-bitline pair; N−1 sub-bitline pairs each having reference cells for selective coupling thereto; (N−2)(N−1) sub-bitline pairs each having generate cells for selective coupling thereto; and sub-bitline pairs being selectively connected in a group through switches such that: the sub-bitlines in the group are precharged to one of a plurality of voltages; one of the (N−1) reference voltages is generated by shorting together sub-bitlines in the group; and the reference voltage is stored in a reference cell in one of the bit-line pairs in the group.

Dependencies are inferred from the claim text.