High bit density, high speed, via and metal programmable read only memory core cell architecture
AssigneeSTMicroelectronics S.r.l.
InventorAnurag Garg
Life of this patent
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Abstract
A high bit density, high speed, via and metal BE type programmable ROM core cell architecture for storing large amounts of non-volatile data and having a relatively fast turn around time is provided. The ROM core cell may include memory cells organized in rows and columns where each of the memory cells includes three transistors and two bit lines. The arrangement between the three transistors and two bit lines may be such that each of the memory cells is capable of storing four bits of data.
Claims42
A BE type programmable read only memory (ROM) comprising:
- a plurality of memory cells organized in rows and columns;
- each of said memory cells comprising three transistors, two word lines, and two bit lines arranged such that said memory cell is capable of storing four bits of data.
A BE type programmable read only memory (ROM) comprising:
- a plurality of memory cells organized in rows and columns, each of said memory cells comprising three transistors and two bit lines arranged such that said memory cell is capable of storing four bits of data, said three transistors of each memory cell being programable according to sixteen different addressing combinations;
- and
- a ground metallization layer to be selectively connected to said transistors.
A method of using a BE type programmable read only memory (ROM) comprising a plurality of memory cells each comprising three transistors, two word lines, and two bit lines, the method comprising:
- storing four data bits in the three transistors of at least one of the memory cells using the two bit lines thereof.
A method of using a BE type programmable read only memory (ROM) comprising a plurality of memory cells, each comprising three transistors and two bit lines, and a ground metallization layer to be selectively connected to the transistors, the method comprising:
- storing four data bits in the three transistors of at least one of the memory cells using the two bit lines thereof and sixteen different addressing combinations.
Dependencies are inferred from the claim text.