Gate voltage testkey for isolation transistor

A memory device having improved subthreshold leakage characteristics comprising:

• a first memory cell;
• a second memory cell;
• an isolation device arranged to reduce leakage between said first and second memory cells, said isolation device comprising an isolation control that is coupled to a select one of at least two bias signals, and
• an antifuse programmable to select the one of said at least two bias signals that is coupled to said isolation control.

A memory device having improved subthreshold leakage characteristics comprising:

• a first memory cell;
• a second memory cell;
• a testkey;
• and
• an isolation device arranged to reduce leakage between said first and second memory cells, wherein said isolation device Is coupled to said testkey and is controlled by a select one of at least two bias signals.

A memory device having improved subthreshold leakage characteristics comprising:

• a first memory cell;
• a second memory cell;
• an isolation device having an Isolation control that is controlled by a select one of at least two bias signals, said isolation device arranged to reduce leakage between said first and second memory cells;
• a testkey;
• a translator having a bias control output coupled to said isolation control of said isolation device, wherein said bias control output carries the selected one of said at least two bias signals to said isolation device;
• and
• at least one control signal coupled between said testkey and said translator, wherein said testkey is arranged to program said bias control output of said translator to said select one of said at least two bias signals.

A memory device having improved subthreshold leakage characteristics comprising:

• a first memory cell comprising:
• a first transistor having a first source/drain region coupled to a bitline, a gate coupled to a first wordline, and a second source/drain region;
• and
• a first capacitor coupling a reference voltage to said second source/drain region;
• a second memory cell comprising:
• a second transistor having a first source/drain region coupled to said bitline, a gate coupled to a second wordline, and a second source/drain region;
• and
• a second capacitor coupling a reference voltage to said second source/drain region;
• an isolation transistor having a first source/drain region coupled to said second source/drain region of said first memory cell, a second source/drain region coupled to said second source/drain region of said second memory cell, and an isolation transistor gate;
• and
• a translator circuit coupled to said isolation transistor gate, said translator circuit programmably configured to couple said isolation transistor gate to a select one of at least two voltages, each of said at least two voltages arranged to turn off said isolation transistor.

A memory device having improved subthreshold leakage characteristics comprising:

• a first memory cell comprising:
• a first transistor having a first source/drain region coupled to a bitline, a gate coupled to a first wordline, and a second source/drain region;
• and
• a first capacitor coupling a reference voltage to said second source/drain region;
• a second memory cell comprising:
• a second transistor having a first source/drain region coupled to said bitline, a gate coupled to a second wordline, and a second source/drain region;
• and
• a second capacitor coupling a reference voltage to said second source/drain region;
• and
• an isolation transistor having a first source/drain region coupled to said second source/drain region of said first memory cell, a second source/drain region coupled to said second source/drain region of said second memory cell, and an isolation transistor gate coupled to a select one of at least two voltages, each of said at least two voltages arranged to turn off said isolation transistor, wherein said isolation transistor gate is further coupled to a testkey that is arranged to change on the fly, which of said at least two voltages couple to said isolation transistor gate.

A memory device having improved subthreshold leakage characteristics comprising:

• a first memory cell comprising:
• a first transistor having a first source/drain region coupled to a bitline, a gate coupled to a first wordline, and a second source/drain region;
• and
• a first capacitor coupling a reference voltage to said second source/drain region;
• a second memory cell comprising:
• a second transistor having a first source/drain region coupled to said bitline, a gate coupled to a second wordline, and a second source/drain region;
• and
• a second capacitor coupling a reference voltage to said second source/drain region;
• an isolation transistor having a first source/drain region coupled to said second source/drain region of said first memory cell, a second source/drain region coupled to said second source/drain region of said second memory cell, and an Isolation transistor gate coupled to a select one of at least two voltages, each of said at least two voltages arranged to turn off said isolation transistor;
• a testkey;
• a translator having a bias control output coupled to said isolation transistor gate said bias control output arranged to couple the selected one of said at least two voltages to said isolation transistor gate;
• and
• at least one control signal coupled between said testkey and said translator, wherein said testkey is arranged to program said bias control output of said translator to said select one of said at least two voltages.

A memory device having improved subthreshold leakage characteristics comprising:

• a plurality of memory cell pairs, each of said memory cell pairs having a first memory cell and a second memory cell;
• an isolation device coupled between adjacent memory cell pairs;
• and
• a translator circuit programmably configured to output a reference signal that is coupled to each isolation device, said translator circuit programmable to set said reference signal to a select one of at least two bias signals, said reference signal arranged to cause each isolation device to reduce leakage between respective ones of said memory cell pairs.