Offset voltage calibration DAC with reduced sensitivity to mismatch errors
AssigneeLattice Semiconductor Corporation
InventorsJames L. Gorecki, Yaohua Yang
Life of this patent
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Abstract
A composite digital-to-analog converter (DAC) includes a first DAC and a second DAC. The first DAC has a first range and a first error. The second DAC has a second range and a second error. The second range of the second DAC is less than the first range of the first DAC. The second range of the second DAC is greater than the first error of the first DAC. The second error of the second DAC is less than the first error of the first DAC. The composite DAC has a composite range and a composite error. The second DAC is coupled to minimize the composite error such that the composite range of the composite DAC is the first range and the composite error of the composite DAC is the second error.
Claims25
A composite digital-to-analog converter (DAC) comprising:
- a first DAC having a first range and a first error;
- a second DAC having a second range and a second error, the second range being less than the first range and greater than the first error, the second error being less than the first error;
- and
- control circuitry for alternately selecting between the first DAC and the second DAC;
- wherein
- the composite DAC has a composite range and a composite error;
- and
- the second DAC is coupled to minimize the composite error such that the composite DAC has the first range and the second error.
An apparatus comprising a composite DAC, the composite DAC comprising:
- a first DAC having a first range and a first error;
- a second DAC having a second range and a second error, the second range being less than the first range and more than the first error;
- the second DAC being coupled to minimize error of the composite DAC such that the composite DAC has the first range and the second error;
- and
- a selection circuit coupled to the first and second DACs for alternately selecting one of the first and second DACs.
A method of minimizing analog circuit offset, the method comprising:
- operating a first DAC to calibrate an analog signal to within a first DAC error of a target value;
- and
- operating a second DAC to calibrate the analog signal to within a second DAC error of the target value after operating the first DAC, the second DAC having a range less than a range of the first DAC and greater than the first DAC error.
Dependencies are inferred from the claim text.