Deserializer

An integrated circuit comprising:

• a word synchronization module for outputting a parallel word based on a first symbol and a second symbol;
• a first single-channel deserializer for outputting said first symbol based on a first serialized stream of bits, wherein said first single-channel deserializer comprises a first plurality of bi-stable storage devices that:
• (i) are clocked out of phase with respect to each other, (ii) are each presented in parallel with said first serialized stream of bits, and (iii) each capture a different bit in said first serialized stream of bits;
• and
• a second single-channel deserializer for outputting said second symbol based on a second serialized stream of bits, wherein said second single-channel deserializer comprises a second plurality of bi-stable storage devices that:
• (i) are clocked out of phase with respect to each other, (ii) are presented in parallel with said second serialized stream of bits, and (iii) each capture a different bit in said second serialized stream of bits.

An integrated circuit comprising:

• a plurality of single-channel deserializers for outputting different symbols in a word, wherein each of said plurality of single-channel deserializers comprises:
• (i) a first bi-stable storage device for receiving a first binary waveform and a first clock signal and for generating a second binary waveform based on said first binary waveform and on said first clock signal;
• (ii) a second bi-stable storage device for receiving said first binary waveform and a second clock signal and for generating a third binary waveform based on said first binary waveform and on said second clock signal;
• and
• (iii) unanimity logic for generating a fourth binary waveform based on a coincidence function of said second binary waveform and said third binary waveform.

An integrated circuit comprising:

• a plurality of single-channel deserializers for outputting different symbols in a word, wherein each of said plurality of single-channel deserializers comprises:
• (i) a first bi-stable storage device for receiving a first binary waveform and a first clock signal and for generating a second binary waveform based on said first binary waveform and on said first clock signal;
• and
• (ii) a second bi-stable storage device for receiving said first binary waveform and a second clock signal and for generating a third binary waveform based on said first binary waveform and on said second clock signal;
• wherein said second clock signal has the same frequency as said first clock signal and said second clock signal has a different phase than said first clock signal.