Fractional-N synthesizer and method of synchronization of the output phase
AssigneeAnalog Devices, Inc.
InventorsMichael F. Keaveney, Colin Lyden
Life of this patent
Estimating the term…
Abstract
A fractional-N synthesizer and method of phase synchronizing the output signal with the input reference signal in a fractional-N synthesizer by generating a synchronization pulse at integer multiples of periods of the input reference signal and gating the synchronization pulse to re-initialize the interpolator in the fractional-N synthesizer to synchronize the phase of the output signal with the input reference signal.
Claims10
A fractional-N synthesizer with synchronised output phase comprising:
- a phase locked loop having an output signal whose frequency is a fractional multiple of the input reference frequency;
- said phase locked loop including a frequency divider;
- a synchronisation counter responsive to said input reference signal for generating synchronisation pulses at integer multiples of M periods of the input reference signal;
- an interpolator responsive to an input fraction to provide to said frequency divider an output which has a fractional value equal to on average, said input fraction;
- and
- a gating circuit responsive to an enable signal to pass at least one of said synchronisation pulses to re-initialise said interpolator to phase synchronise said output signal with respect to the input reference signal.
A method of phase synchronising the output signal with the input reference signal in a fractional-N synthesiser having an interpolator, comprising:
- generating a synchronisation pulse at integer multiples of periods of the input reference signal;
- and
- gating said synchronisation pulse to re-initialise the interpolator in the fractional-N synthesiser to synchronise the phase of the output signal with the input reference signal.
A fractional synthesiser with synchronised output phase comprising:
- a phase locked loop having an output signal whose frequency is a fractional multiple of the input reference frequency;
- said phase locked loop including a frequency divider;
- a synchronisation counter responsive to said input reference signal for generating synchronisation pulses at integer multiples of M periods of the input reference signal;
- an interpolator responsive to an input fraction to provide to said frequency divider an output which has a fractional value equal to on average, said input fraction;
- a gating circuit responsive to an enable signal to pass at least one of said synchronisation pulses to re-initialise said interpolator to phase synchronise said output signal with respect to the input reference signal;
- and
- a programmable divider circuit and a summing circuit responsive to said interpolator output and an integer input.
A fractional synthesiser with synchronised output phase comprising;
- a phase locked loop having an output signal whose frequency is a fractional multiple of the input reference frequency;
- said phase locked loop including a frequency divider;
- a synchronisation counter responsive to said input reference signal for generating synchronisation pulses at integer multiples of M periods of the input reference signal;
- an interpolator responsive to an input fraction to provide to said frequency divider an output which has a fractional value equal to on average, said input fraction;
- a gating circuit responsive to an enable signal to pass at least one of said synchronisation pulses to re-initialise said interpolator to phase synchronise said output signal with respect to the input reference signal;
- and
- said gating circuit passes the second or later synchronisation pulse after the occurrence of the enable signal.
Dependencies are inferred from the claim text.