Differential amplifying circuit and multi-stage differential amplifying circuit using the same
AssigneeNEC Electronics Corporation
InventorYasufumi Suzuki
Life of this patent
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AssigneeNEC Electronics Corporation
InventorYasufumi Suzuki
Estimating the term…
A multi-stage differential amplifying circuit (100) is disclosed. Multi-stage differential amplifying circuit (100) may include initial stage differential amplifying circuits (SN1 and SP1). Initial stage amplifying circuits (SN1 and SP1) may receive an input signal at input terminals (H01 and H02) and provide a differential output signal at nodes (N9 and N13). An amplitude controlling transistor (ND) may provide a controllable impedance path between nodes (N9 and N13). Amplitude controlling transistor (ND) may have a control gate connected to a current supply node (N10). The controllable impedance path may be controlled so that a magnitude of a differential output signal at nodes (N9 and N13) may be more consistent even when an offset voltage of an input signal at input terminals (H01 and H02) varies. A next stage differential amplifying circuit (SOP) may receive the differential output signal at nodes (N9 and N13) and provide an output signal at an output terminal (N01).
A differential amplifying circuit, comprising:
A multi-stage differential amplifying circuit, comprising:
A differential amplifying circuit, comprising:
Dependencies are inferred from the claim text.