Semiconductor integrated circuit
AssigneeMitsubishi Denki Kabushiki Kaisha
InventorsHiromi Notani, Hiroshi Makino
Life of this patent
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AssigneeMitsubishi Denki Kabushiki Kaisha
InventorsHiromi Notani, Hiroshi Makino
Estimating the term…
On a sleep state, a voltage dropping circuit 2 supplies a power supply line VA1 with a voltage obtained by dropping a voltage of a power supply line VA2, instead of a voltage in accordance with ON state of a switch QA1. A power supply line GND has a voltage equal to the ground voltage. A charge pump circuit 10 outputs the ground voltage on an active state. The charge pump circuit 10 outputs a voltage which is lower than the ground voltage, on the sleep state. A source electrode and a substrate electrode are connected to the power supply lines VA1 and VA2 in each of PMOS transistors Q3 and Q4 of an internal circuit 1 (latch circuit), respectively. A source electrode is connected to the power supply line GND in each of nMOS transistors Q5 and Q6 of the internal circuit 1. A substrate electrode is supplied with the voltage which is outputted from the charge pump circuit, in each of the nMOS transistors Q5 and Q6 of the internal circuit 1. As a result, it is possible to reduce a leakage current withholding data in the internal circuit on the sleep state, even if the supply voltage drops on the sleep state.
A semiconductor integrated circuit comprising:
Dependencies are inferred from the claim text.