Latch structures and systems with enhanced speed and reduced current drain

In a latch that transitions from an acquire mode to a latch mode in response to a latch command signal and has cross-coupled first and second isolation transistors that have first and second current terminals with said first current terminals coupled to receive a differential input signal, cross-coupled first and second latch transistors that provide collectors, and first and second current-limiting transistors that are each coupled between a respective one of said second current terminals and a respective one of said collectors and that each provide an impedance that transitions from an acquire impedance to a greater latch impedance in response to a respective one of control signals Scntrl;

• the improvement comprising:
• at least one of first and second shorting transistors that are respectively coupled between said second current terminals and between said collectors and that each transition from a shorting impedance to a greater isolating impedance in response to said latch command signal;
• and
• a controller that responds to complementary metal-oxide-semiconductor (CMOS) signals and is coupled to receive CMOS-level sense signals Ssns from at least one of said second current terminals and, in response, provide at least one of said control signals Scntrl.

In an analog-to-digital converter that converts an analog input signal to a corresponding digital output signal in response to a latch command signal and has cross-coupled first and second isolation transistors that have first and second current terminals with said first current terminals coupled to receive a differential input signal, cross-coupled first and second latch transistors that provide collectors, and first and second current-limiting transistors that are each coupled between a respective one of said second current terminals and a respective one of said collectors and that each provide an impedance that transitions from an acquire impedance to a greater latch impedance in response to a respective one of control signals Scntrl;

• the improvement comprising:
• a sampler that provides a sample of said analog input signal;
• a resistor ladder that provides a plurality of reference signals;
• comparators that generate comparison signals in response to said sample and said reference signals;
• latches that provide latched output signals in response to said comparison signals and said latch command signal;
• and
• an encoder that generates said digital output signal in response to said latched output signals;
• wherein each of said latches transitions from an acquire mode to a latch mode in response to said latch command signal and includes:
• a) at least one switch coupled to provide currents to said first current terminals in response to said latch command signal;
• and
• b) a controller that responds to complementary metal-oxide-semiconductor (CMOS) signals and is coupled to receive CMOS-level sense signals Ssns from at least one of said second current terminals and, in response, provide at least one of said control signals Scntrl.

In an analog-to-digital converter that converts an analog input signal to a corresponding digital output signal in response to a latch command signal and has cross-coupled first and second isolation transistors that have first and second current terminals with said first current terminals coupled to receive a differential input signal, cross-coupled first and second latch transistors that provide collectors, and first and second current-limiting transistors that are each coupled between a respective one of said second current terminals and a respective one of said collectors and that each provide an impedance that transitions from an acquire impedance to a greater latch impedance in response to a respective one of control signals Scntrl;

• the improvement comprising:
• a sampler that provides a sample of said analog input signal;
• a resistor ladder that provides a plurality of reference signals;
• comparators that generate comparison signals in response to said sample and said reference signals;
• latches that provide latched output signals in response to said comparison signals and said latch command signal;
• and
• an encoder that generates said digital output signal in response to said latched output signals;
• wherein each of said latches transitions from an acquire mode to a latch mode in response to said latch command signal and includes:
• a) at least one of first and second shorting transistors that are respectively coupled between said second current terminals and between said collectors and that each transition from a shorting impedance to a greater isolating impedance in response to said latch command signal;
• and
• b) a controller that responds to complementary metal-oxide-semiconductor (CMOS) signals and is coupled to receive CMOS-level sense signals Ssns from at least one of said second current terminals and, in response, provide at least one of said control signals Scntrl.