Power on reset circuit
AssigneeMitsubishi Denki Kabushiki Kaisha
InventorsShigeki Ohbayashi, Tadayuki Shimizu
Life of this patent
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Abstract
In a power on reset (POR) circuit, when power is turned on, an output signal of an inverter attains an H level and an N channel MOS transistor is rendered conductive. The potential of an input node of the inverter becomes a potential of a power supply voltage divided by a conductive resistance value R1 of a P channel MOS transistor and a conductive resistance value R2 of an N channel MOS transistor. Assuming that the threshold voltage of the inverter is 0.8 V and R1:R2=2:3, then the power supply voltage Vres at the time when signal POR# inverts its level becomes 1.33 V. Thus, this POR circuit can reliably be utilized even in a product designed to operate with 1.5 V incorporating a MOS transistor having a threshold voltage of 0.8 V.
Claims2
A power on reset circuit incorporated in a semiconductor device and generating a reset signal for resetting said semiconductor device when power is turned on, comprising:
- an inverter driving said reset signal to an activated level in response to reception of a power supply potential and a reference potential, and driving said reset signal to an inactivated level in response to a potential of an input node of the inverter exceeding a predetermined threshold potential;
- a first resistance element having one electrode receiving said power supply potential and another electrode connected to the input node of said inverter;
- a first transistor of a first conductivity type having a first electrode receiving said reference potential and a second electrode connected to the input node of said inverter, and rendered conductive in response to said reset signal attaining the activated level;
- and
- a second transistor of the first conductivity type having a first electrode receiving said power supply potential and a second electrode connected to the input node of said inverter;
- a second resistance element having one electrode receiving said power supply potential and another electrode connected to an input electrode of said second transistor;
- and
- a capacitor having one electrode receiving said reference potential and another electrode connected to the input electrode of said second transistor.
Dependencies are inferred from the claim text.