Method and apparatus for using parasitic effects in processing high speed signals

An integrated circuit system for processing high speed signals, the integrated circuit system comprising:

• a first building block receiving an input signal having a frequency and producing an output signal;
• a second building block coupled to the first building block and receiving the output signal therefrom, wherein each of the two building blocks includes:
• a number of transistors, each associated with a value of an Electrically Equivalent Channel Geometry (EECG) determining parasitic capacitances around the each of the transistors;
• wherein a ratio for each of the transistors is determined to be the value of the EECG of each of the transistors over the value of the EECG of a chosen one of the transistors;
• and
• when the ratio for each of the transistors in the first building block is adjusted in reference to the frequency so that the parasitic capacitances are inherently and properly formed to create parasitic effects to minimize possible artifacts in the output from the first building block.

A method for processing high speed signals, the method comprising:

• determining a frequency in an input signal to be received at a first difference circuit, providing a second difference circuit coupled to the first difference circuit, each of the first and second difference circuits including a number of transistors, each of the transistors associated with a value of an Electrically Equivalent Channel Geometry (EECG) determining parasitic capacitances around the each of the transistors;
• determining a ratio for each of the transistors, wherein the ratio is determined to be the value of the EECG of the each of the transistors over the value of the EECG of a chosen one of the transistors;
• and
• adjusting the ratio for each of the transistors in reference to the frequency so that the parasitic capacitances are inherently and properly formed.