Digital designs optimized with time division multiple access technology

A system comprising:

• a logic circuit having state logic, wherein the state logic function is provided by a multiphase state saving circuit having a selectable output phase;
• and
• logic circuitry to provide selection of the output phase, wherein the logic circuitry comprises at least one time division multiple access (TDMA) cell.

A system comprising:

• a logic circuit having state logic, wherein the state logic function is provided by a multiphase state saving circuit having a selectable output phase;
• and
• logic circuitry to provide selection of the output phase, wherein the logic circuitry comprises at least one scannable pipelined register (SPR) cell.

A system comprising:

• a logic circuit having combinatorial and state logic, the logic circuit selectively configurable as a single phase circuit or a multi-phase circuit, the single phase circuit implementing a function and operating at a first rate, each phase of the multi-phase circuit implementing the function and operating at a lesser rate wherein the sum of the lesser rates is less than or equal to the first rate, the state logic function provided by a multiphase state saving circuit having a selectable output phase such that the plural phases can be provided in the logic circuit without having to duplicate the combinatorial logic;
• and
• logic circuitry to provide selection of the output phase wherein the logic circuitry comprises at least one time division multiple access (TDMA) cell.

A system comprising:

• a logic circuit having combinatorial and state logic, the logic circuit selectively configurable as a single phase circuit or a multi-phase circuit, the single phase circuit implementing a function and operating at a first rate, each phase of the multi-phase circuit implementing the function and operating at a lesser rate wherein the sum of the lesser rates is less than or equal to the first rate, the state logic function provided by a multiphase state saving circuit having a selectable output phase such that the plural phases can be provided in the logic circuit without having to duplicate the combinatorial logic;
• and
• logic circuitry to provide selection of the output phase wherein the logic circuitry comprises at least one scannable pipelined register cell.