Asynchronous latch design for field programmable gate arrays

A method of replacing a look-up table in an FPGA, said method comprising the steps of:

• designating a conventional latch element as a present dominant transparent latch (PDTL);
• supplying a first data signal to a data input of said PDTL;
• supplying a second data signal to a present input of said PDTL;
• and
• supplying a constant signal to a clock input of said PDTL.

A programmable logic circuit, comprising:

• an array of programmable latch elements, at least one of said latch elements having a data input and a preset input and adapted to form a preset dominant transparent latch;
• and
• a first data signal coupled to said data input and a second data signal coupled to said preset input, each said data signal representing logic input data and wherein said preset dominant transparent latch generating a desired output signal based on said data signals,
• said latch element further comprising a clock input, said clock input being coupled to a constant input signal.

A field-programmable gate array (FPGA), comprising:

• an array of programmable latch elements, at least one of said latch elements having a data input, a clock input and a preset input;
• and
• an array of programmable flip-flop elements generating at least a first and second flip-flop output signals;
• wherein at least one of said latch elements being adapted to form a preset dominant transparent latch (PDTL) wherein said first flip-flop output signal is coupled to said data input, said second flip-flop output signal is coupled to said preset input, and said clock input is held constant, and wherein said PDTL being used in place of a conventional look-up table to generate a desired output signal.