FPGA with improved structure for implementing large multiplexers
AssigneeXilinx, Inc.
InventorAlireza S. Kaviani
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Abstract
Novel structures for implementing wide multiplexers from user designs in FPGA CLBs. Input multiplexers providing the function generator data input signals are modified to function not just based on values stored in configuration memory cells, but also under the control of user signals. Thus, the input multiplexers of the invention are much more flexible than traditional input multiplexers. In one embodiment, the improved data input multiplexer is provided on two of four data input terminals of the function generator, enabling the implementation of an 8-to-1 multiplexer using only a single function generator. Another embodiment applies the concept of mixed memory cell and user control of a multiplexer to the general interconnect structure of an FPGA.
Claims10
A configurable logic block (CLB) in a Field Programmable Gate Array (FPGA), the FPGA comprising a general interconnect structure and a plurality of the CLBs, the CLB comprising:
- a function generator having a plurality of data input terminals;
- first and second bypass input multiplexers each having a plurality of input terminals coupled to the general interconnect structure and each further having an output terminal coupled to bypass the function generator data input terminals;
- and
- a first data input multiplexer coupled between the general interconnect structure and a first one of the data input terminals of the function generator, the first data input multiplexer comprising:
- a plurality of data input terminals coupled to the general interconnect structure;
- a decoder circuit having a plurality of input terminals coupled to the output terminals of the first and second bypass multiplexers and further having a plurality of output terminals;
- and
- a second stage multiplexer having a plurality of select terminals coupled to the output terminals of the decoder circuit, a plurality of data input terminals coupled to the data input terminals of the first data input multiplexer, and an output terminal coupled to a first one of the data input terminals of the function generator.
Dependencies are inferred from the claim text.