Method and apparatus for non-linear termination of a transmission line

An active termination circuit for terminating a signal traversing on a transmission line of an electronic device, comprising:

• a bottom clamping transistor coupled to a first potential having a bottom clamping transistor control node arranged for clamping said signal at about a first reference voltage;
• a bottom threshold reference transistor coupled to a first reference voltage supply configured to supply the first reference voltage, wherein the bottom threshold reference transistor provides a first bias voltage to said bottom clamping transistor control node that biases said bottom clamping transistor control node at about a first threshold voltage above said first reference voltage, said first threshold voltage representing a threshold voltage of said bottom clamping transistor;
• a top clamping transistor coupled to a second potential having a top clamping transistor control node arranged for clamping said signal at about a second reference voltage;
• a top threshold reference transistor coupled to a second reference voltage supply configured to supply the second reference voltage, wherein said top threshold reference transistor provides a second bias voltage to said top clamping transistor control node that biases said top clamping transistor control node at about a second threshold voltage below said second reference voltage, said second threshold voltage representing a top clamping transistor threshold voltage;
• an inverter unit having an inverter unit input node coupled to the transmission line and an inverter unit output node;
• a first resistor coupled between said bottom clamping transistor control node and the inverter unit output node;
• and
• a second resistor coupled between said top clamping transistor control node and the inverter unit output node.

An active termination circuit for terminating a signal traversing on a transmission line of an electronic device, comprising:

• a bottom clamping transistor coupled to a first potential having a bottom clamping transistor control node arranged for clamping said signal at about a first reference voltage;
• a bottom threshold reference transistor coupled to a first reference voltage supply configured to supply the first reference voltage, wherein the bottom threshold reference transistor provides a first bias voltage to said bottom clamping transistor control node that biases said bottom clamping transistor control node at about a first threshold voltage above said first reference voltage, said first threshold voltage representing a threshold voltage of said bottom clamping transistor;
• a top clamping transistor coupled to a second potential having a top clamping transistor control node arranged for clamping said signal at about a second reference voltage;
• a top threshold reference transistor coupled to a second reference voltage supply configured to supply the second reference voltage, wherein said top threshold reference transistor provides a second bias voltage to said top clamping transistor control node that biases said top clamping transistor control node at about a second threshold voltage below said second reference voltage, said second threshold voltage representing a top clamping transistor threshold voltage;
• a first inverter unit having a first inverter unit impedance and a first inverter unit input connected to the transmission line and a first inverter unit output connected to the bottom clamping transistor control gate node;
• and
• a second inverter unit having a second inverter unit impedance and a second inverter unit input connected to the transmission line and a second inverter unit output connected to the top clamping transistor control gate node, wherein the first inverter unit impedance and the second inverter unit impedance form a voltage divider circuit.

An active termination circuit for terminating a signal traversing on a transmission line of an electronic device, comprising:

• a bottom clamping transistor coupled to a first potential having a bottom clamping transistor control node arranged for clamping said signal at about a first reference voltage;
• a bottom threshold reference transistor coupled to a first reference voltage supply configured to supply the first reference voltage, wherein the bottom threshold reference transistor provides a first bias voltage to said bottom clamping transistor control node that biases said bottom clamping transistor control node at about a first threshold voltage above said first reference voltage, said first threshold voltage representing a threshold voltage of said bottom clamping transistor;
• a top clamping transistor coupled to a second potential having a top clamping transistor control node arranged for clamping said signal at about a second reference voltage;
• a top threshold reference transistor coupled to a second reference voltage supply configured to supply the second reference voltage, wherein said top threshold reference transistor provides a second bias voltage to said top clamping transistor control node that biases said top clamping transistor control node at about a second threshold voltage below said second reference voltage, said second threshold voltage representing a top clamping transistor threshold voltage;
• an inverter unit having an inverter unit input node coupled to the transmission line and an inverter unit output node;
• a first capacitor coupled between said bottom clamping transistor control node and the inverter unit output node;
• and
• a second capacitor coupled between said top clamping transistor control node and the inverter unit output node.