Impedance adjustment circuit

An impedance adjustment circuit comprising:

• a reception-side semiconductor device including at least one terminal resistor, said impedance adjustment circuit achieving impedance matching between said terminal resistor and a transmission line;
• a reference resistor external to said reception-side semiconductor device, said reference resistor having a first resistance which is proportional to characteristic impedance of the transmission line, wherein
• said terminal resistor has a second resistance and an ON resistance of an MOS transistor, and
• resistance of said terminal resistor is adjusted by referring to said reference resistor;
• a reference voltage generation unit which generates a reference voltage in spite of variations in power supply voltage, temperature, and manufacturing process;
• a voltage control unit which changes the reference voltage to generate a standard voltage;
• an external resistor connection unit, which biases a first terminal of said reference resistor, a second terminal of which is connected to the ground, to the standard voltage to generate a standard current flowing in said reference resistor;
• a first mirror circuit unit which generates a first current equal to the standard current by using a combination of said terminal resistor having the second resistance and the ON resistance of said MOS transistor biased to operate in a linear region;
• and
• a second mirror circuit unit including a terminal resistor having the same configuration as the combination of said MOS transistor and said terminal resistor as a pull-up resistor of the transmission line, wherein said second mirror circuit unit generates a second current equal to the standard current and the first standard current using said terminal resistor.

An impedance adjustment circuit comprising:

• a reception-side semiconductor device including at least one terminal resistor, said impedance adjustment circuit achieving impedance matching between said terminal resistor and a transmission line;
• a reference resistor external to said reception-side semiconductor device, said reference resistor having a first resistance which is proportional to characteristic impedance of the transmission line, wherein
• said terminal resistor has a second resistance and an ON resistance of an MOS transistor, and
• resistance of said terminal resistor is adjusted by referring to said reference resistor;
• a reference voltage generation unit which generates a reference voltage in spite of variations in power supply voltage, temperature, and manufacturing process;
• a voltage control unit which changes the reference voltage to generate a standard voltage;
• a voltage shift unit which shifts voltage levels of differential input signals and the standard voltage to match the voltage levels and the standard voltage to an input range;
• a common potential extraction unit for extracting a common potential from the voltage levels of the differential input signals shifted by the voltage shift unit;
• a voltage power supply to which a first terminal of said reference resistor is connected;
• an external resistor connection unit which biases a second terminal of said reference resistor to the standard voltage to generate a standard current flowing in said reference resistor;
• a differential circuit unit which generates a current corresponding to the common potential and a current corresponding to the standard voltage according to the difference between the common potential and the standard voltage;
• a common-side current mirror unit which generates a first current equal to the current corresponding to the reference voltage;
• a mirror circuit unit which generates a second current, equal to the current corresponding to the standard voltage and the first current, for reflecting a variation of the common potential, which generates a third current that is ½ the standard current, reflecting a variation of the characteristic impedance of the transmission line, and which adjusts a bias voltage of said MOS transistor such that a combined resistance of said terminal resistor having the second resistance and the ON resistance of said MOS transistor biased to operate a linear region is constant even though the common potential and the characteristic impedance of the transmission line vary;
• and
• an input impedance circuit unit which uses a terminal resistor having the same configuration as the combination of said terminal resistor having the second resistance and said ON resistance of said MOS transistor as a pull-up resistor of the transmission line.

An impedance adjustment circuit comprising:

• a reception-side semiconductor device including at least one terminal resistor, said impedance adjustment circuit achieving impedance matching between said terminal resistor and a transmission line;
• a reference resistor external to said reception-side semiconductor device, said reference resistor having a first resistance which is proportional to characteristic impedance of the transmission line, wherein
• said terminal resistor has an ON resistance of an MOS transistor, and
• resistance of said terminal resistor is adjusted by referring to said reference resistor;
• a reference voltage generation unit which generates a reference voltage in spite of variations in power supply voltage, temperature, and manufacturing processes;
• a voltage control unit which changes the reference voltage to generate a standard voltage;
• a voltage power supply to which a first terminal of said reference resistor is connected;
• an external resistor connection unit which biases a second terminal of said reference resistor to the standard voltage to generate a standard current flowing in said reference resistor;
• a first mirror circuit unit which generates a first current equal to the standard current by using an ON resistance of said MOS transistor biased to operate in a linear region;
• and
• a second mirror circuit unit which uses a terminal resistor having the same configuration as said MOS transistor as a pull-up resistor of the transmission line, wherein said second mirror circuit unit generates a second current equal to the standard current and the first standard current using said terminal resistor.