Low profile stack semiconductor package

A low profile stack semiconductor package, comprising:

• a substrate having an upper surface and a lower surface opposed to the upper surface, wherein an opening is formed to penetrate through the upper and lower surfaces of the substrate;
• a first chip having an active surface formed with a plurality of centrally-situated bond pads thereon, and a non-active surface opposed to the active surface, wherein the active surface of the first chip is mounted on the upper surface of the substrate in a manner that, the centrally-situated bond pads are exposed to the opening of the substrate;
• a second chip having an active surface formed with a plurality of centrally-situated bond pads thereon, and a non-active surface opposed to the active surface, wherein a cushion member is formed at peripheral area on the active surface, and extends outwardly beyond a peripheral edge of the active surface, allowing a portion of the cushion member to protrude beyond an edge side of the second chip, and wherein the non-active surface of the second chip is mounted on the non-active surface of the first chip;
• a plurality of first bonding wires for electrically connecting the bond pads of the first chip to the lower surface of the substrate;
• a plurality of second bonding wires for electrically connecting the bond pads of the second chip to the upper surface of the substrate in a manner that, the second bonding wires are adapted to be in contact with at least the protruding portion of the cushion member, beyond which the second bonding wires turn to be directed toward the upper surface of the substrate;
• an encapsulant for encapsulating the first and second chips, and the first and second bonding wires;
• and
• a plurality of solder balls implanted on the lower surface of the substrate, for electrically connecting the first and second chips to an external device.

A low profile stack semiconductor package, comprising:

• a substrate having an upper surface and a lower surface opposed to the upper surface, wherein an opening is formed to penetrate through the upper and lower surfaces of the substrate;
• a first chip having an active surface formed with a plurality of centrally-situated bond pads thereon, and a non-active surface opposed to the active surface, wherein the active surface of the first chip is mounted on the upper surface of the substrate in a manner that, the centrally-situated bond pads are exposed to the opening of the substrate;
• a second chip having an active surface formed with a plurality of centrally-situated bond pads thereon, and a non-active surface opposed to the active surface, wherein a cushion member is formed at peripheral area on the active surface, and extends outwardly and downwardly to entirely cover an edge corner at the active surface and to reach an edge side of the second chip, in a manner that an edge corner of the cushion member is situated outwardly in elevation above the edge corner of the second chip, and wherein the non-active surface of the second chip is mounted on the non-active surface of the first chip;
• a plurality of first bonding wires for electrically connecting the bond pads of the first chip to the lower surface of the substrate;
• a plurality of second bonding wires for electrically connecting the bond pads of the second chip to the upper surface of the substrate in a manner that, the second bonding wires are adapted to be in contact with at least the edge corner of the cushion member, beyond which the second bonding wires turn to be directed toward the upper surface of the substrate;
• an encapsulant for encapsulating the first and second chips, and the first and second bonding wires;
• and
• a plurality of solder balls implanted on the lower surface of the substrate, for electrically connecting the first and second chips to an external device.