Semiconductor package leadframe assembly and method of manufacture

A packaged semiconductor comprising:

• a chip paddle adapted to support a semiconductor chip thereupon and having a receiving area;
• a semiconductor chip coupled to the receiving area and provided with a plurality of bond pads;
• means for bonding said semiconductor chip to said chip paddle;
• a plurality of tie bars externally extended from corners of said chip paddle;
• a plurality of internal leads located at regular intervals along a perimeter of said chip paddle;
• conductive wires electrically connecting the bond pads of the semiconductor chip to said internal leads;
• a package body in which said semiconductor chip, the chip paddle, the tie bars, the internal leads and the conductive wires are encapsulated by an encapsulation material while said chip paddle, said tie bars and said internal leads are externally exposed at their bottom surfaces, and
• at least one of said tie bars being constructed with a reverse-down set portion formed adjacent the chip paddle and outside of a perimeter of the chip paddle to create a space between the at least one tie bar and adjacent ones of the plurality of leads and for minimizing short circuiting between the at least one tie bar and the plurality of leads
• wherein the reverse-down set portion reduces an area of the externally exposed portion of the respective tie bar.

A semiconductor package of the type adapted for receiving a semiconductor chip and wherein said semiconductor chip has a plurality of bond pads, said semiconductor package comprising:

• a chip paddle adapted to support the semiconductor chip thereupon and for providing a bonding surface;
• a plurality of tie bars extending outwardly from the corners of said chip paddle;
• a plurality of internal leads located at regular intervals along a perimeter of said chip paddle;
• conductive wires for electrically connecting the bond pads of the semiconductor chip to said plurality of internal leads;
• a package body in which said semiconductor chip, the chip paddle, the tie bars, the internal leads and the conductive wires are encapsulated by an encapsulation material while said chip paddle, the said tie bars and said internal leads are externally exposed at their bottom surfaces;
• and
• at least one of said tie bars being constructed with a reverse-down set portion formed adjacent the chip paddle and outside of a perimeter of the chip paddle for minimizing short circuiting between the at least one tie bar and the plurality of leads;
• wherein the reverse-down set portion reduces an area of the externally exposed portion of the respective tie bar.

A leadframe adapted for securement within an encapsulation material for the containment of a semiconductor chip mounted thereto, said leadframe comprising:

• a chip paddle adapted for the receipt of said semiconductor chip thereupon;
• a frame disposed about the periphery of said chip paddle and spaced therefrom;
• a plurality of tie bars extending between said chip paddle and said frame for the interconnection thereof;
• and
• wherein at least one of said tie bars is formed with a reverse-down set portion therein for securing said at least one tie bar within said encapsulation material and for preventing the exposure of said at least one tie bar in select portions of said semiconductor package.