US 6,555,877 B2 · NMOSFET with negative voltage capability formed in P-type substrate and method of making the same

Abstract

A semiconductor device (10,50) is disclosed which can accommodate a negative voltage on its source using a P-type substrate (12) which is connected to ground potential. A first embodiment illustrates a device which can handle high voltage applications as well as a negative voltage applied to the source. A drain contact region (29) is recessed by a dimension (X) from a first insulated region (18). The dimension (X) provides for an optimum distance for high voltage applications while avoiding lateral surface punch-through. A second embodiment illustrates a gate structure (52) having a shape which surrounds a drain contact region (62) and accommodates a high voltage application while also eliminating the lateral surface punch-through. The drain contact region (62) is formed in a P-type region (20) centered inside the gate structure (52).

Claims7

Dependent claims

A lateral semiconductor device substantially eliminating lateral surface punch through, comprising:

a first well region of a first conductivity type formed in a first surface of a substrate;
a second well region of a second conductivity type formed within the first well region;
a drain region of the first conductivity type formed within the second well region;
a first insulating region formed adjacent to the drain region on the first surface of the substrate, wherein a minimum lateral distance separating the nearest first insulating region from the drain region is established to substantially eliminate lateral surface punch through.

1 more element

Dependencies are inferred from the claim text.

NMOSFET with negative voltage capability formed in P-type substrate and method of making the same

Life of this patent

NMOSFET with negative voltage capability formed in P-type substrate and method of making the same

Life of this patent

Abstract

Claims7