Thin film transistor array substrate having laser illumination indicator

A thin film transistor array substrate comprising:

• a transparent insulating substrate;
• a first signal line formed on the insulating substrate;
• a second signal line formed on the insulating substrate, the second signal line crossing over the first signal line while being insulated from the first signal line;
• a signal line assembly including a base line and a plurality of branch lines branched from the base line, the base line crossing over the second signal line while being insulated from the second signal line;
• a bridge interconnecting parts of the signal line assembly placed at both sides of the first signal line while being insulated from the first signal line;
• a thin film transistor connected to the first and the second signal lines;
• and
• a pixel electrode connected to the thin film transistor,
• wherein the signal line assembly includes a plurality of indicators for indicating locations of laser illumination during repairing line, failures at the first signal line or the second signal line.

A thin film transistor array substrate comprising:

• an insulating substrate;
• a gate line assembly formed on the insulating substrate, the gate line assembly including a gate line extending in the horizontal direction and a gate electrode connected to the gate line;
• a storage electrode line assembly formed on the insulating substrate, the storage electrode line assembly including a storage electrode line extending parallel to the gate line, and a plurality of storage electrodes branched from the storage electrode line while extending in the vertical direction;
• a gate insulating layer covering the gate line assembly and the storage electrode line assembly;
• a semiconductor layer formed on the gate insulating layer while being partially overlapped with the gate electrode;
• a data line assembly including a data line formed on the gate insulating layer while extending in the vertical direction, a source electrode connected to the data line while being partially placed over the semiconductor layer, and a drain electrode facing the source electrode while being partially placed over the semiconductor layer;
• a passivation layer covering the data line assembly and the semiconductor layer having a first contact hole exposing the drain electrode, a second contact hole exposing the storage electrode, and a third contact hole exposing the storage electrode line;
• a pixel electrode formed on the passivation layer while being connected to the drain electrode through the first contact hole;
• and
• a bridge formed on the passivation layer while interconnecting the storage electrode and the storage electrode line placed at both sides of the gate line through the second and the third contact holes,
• wherein the plurality of storage electrodes and the storage electrode line include a plurality of indicators placed close to the second and the third contact holes for indicating locations of laser illumination for repairing line failures.

A thin film transistor array substrate comprising:

• an insulating substrate;
• a gate line assembly formed on the insulating substrate, the gate line assembly having a gate line extending in the horizontal direction, and a gate electrode connected to the gate line;
• a storage electrode line assembly formed on the insulating substrate, the storage electrode line assembly including a storage electrode line extending parallel to the gate line, and a plurality of storage electrodes branched from the storage electrode line while extending in the vertical direction;
• a gate insulating layer covering the gate line assembly and the storage electrode line assembly;
• a semiconductor layer formed on the gate insulating layer while being partially overlapped with the gate electrode;
• a data line assembly including a data line formed on the gate insulating layer while extending in the vertical direction, a source electrode connected to the data line while being partially placed over the semiconductor layer, and a drain electrode partially placed on the semiconductor layer while facing the source electrode;
• a passivation layer covering the data line assembly and the semiconductor layer, the passivation layer having first contact hole exposing the drain electrode, second contact hole exposing the storage electrode, and third contact hole exposing the storage electrode line;
• a pixel electrode formed on the passivation layer, the pixel electrode being connected to the drain electrode through the first contact hole;
• and
• a bridge formed on the passivation layer while interconnecting the storage electrode and the storage electrode line placed at both sides of the gate line through the second and third contact holes;
• wherein a plurality of indicators are provided between the portions of the storage electrode line and the storage electrode overlapped with the bridge, and the portion of the storage electrode line and the storage electrode overlapped with the pixel electrode.