Flash memory gate coupling using HSG polysilicon
AssigneeAdvanced Micro Devices, Inc.
InventorUnsoon Kim
Life of this patent
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Abstract
A method for improving the gate coupling in a flash memory core includes forming floating gates of memory element stacks by depositing a first polysilicon layer having relatively small grain size on a tunnel oxide layer and then depositing a second polysilicon layer on the first, the second polysilicon layer being made of relatively large hemispherical-grained (HSG) polysilicon crystals, which improves gate coupling. In contrast, owing to the relatively small size of its grains, the first layer of polysilicon advantageously establishes a relatively flat surface interface with the tunnel oxide layer that is between the memory stacks and the underlying silicon substrate. Conventional control gates are then established above the HSG layer.
Claims6
A flash memory wafer, comprising:
- a core memory region including at least one silicon substrate;
- and
- plural stacks in the core memory region, each stack having at least one respective polysilicon layer on a tunnel oxide layer and at least one HSG layer above the polysilicon layer each stack also having at least one sidewall layer, the HSG layer overlapping and contacting the sidewall layer.
A flash memory wafer, comprising:
- a core memory region including at least one silicon substrate;
- and
- plural stacks in the core memory region, each stack having at least one respective polysilicon layer on a tunnel oxide layer and at least one HSG layer above the polysilicon layer, each stack also having at least one sidewall layer below and in contact with the HSG layer.
Dependencies are inferred from the claim text.