Back to results
US 6,555,839 B2Granted
Buried channel strained silicon FET using a supply layer created through ion implantation
AssigneeAmberWave Systems Corporation
InventorEugene A. Fitzgerald
Life of this patent
Estimating the term…
Abstract
A circuit including at least one strained channel, enhancement mode FET, and at least one strained channel, depletion mode FET. The depletion mode FET includes an ion implanted dopant supply. In exemplary embodiments, the FETs are surface channel or buried channel MOSFETS. In another exemplary embodiment, the FETs are interconnected to form an inverter.
Claims14
A circuit comprising:
- a substantially relaxed SiGe layer;
- at least one strained channel, enhancement mode FET formed on said substantially relaxed SiGe layer;
- and
- at least one strained channel, depletion mode FET formed on said substantially relaxed SiGe layer, wherein
- said depletion mode FET comprises an ion implanted dopant supply.
2 more elements
An inverter comprising:
- a substantially relaxed SiGe layer;
- a strained buried channel depletion mode FET formed on said substantially relaxed-SiGe layer;
- and
- a strained surface channel enhancement mode FET formed on said substantially relaxed SiGe layer, wherein
- said strained buried channel depletion mode FET comprises an ion implanted dopant supply.
2 more elements
An inverter comprising:
- a substantially relaxed SiGe layer;
- a strained buried channel depletion mode MOSFET formed on said substantially relaxed SiGe layer;
- and
- a strained surface channel enhancement mode MOSFET formed on said substantially relaxed SiGe layer, wherein
- said strained buried channel depletion mode MOSFET comprises an ion implanted dopant supply.
2 more elements
Dependencies are inferred from the claim text.