Interconnect structure

An integrated circuit formed by a method of forming interconnects which comprises:

• cleaning vias formed on a wafer;
• filling vias and forming metalized bond pads;
• forming compliant, conductive bumps on the metalized bond pads;
• at least partially surrounding the compliant, conductive bumps in a supporting layer;
• delineating the compliant, conductive bumps;
• forming eutectic solder or solder alloy bumps over the compliant, conductive bumps;
• singulating integrated circuits from the wafer;
• and
• bonding the singulated integrated circuits to a printed circuit board.
• 17.The integrated circuit of claim 16 wherein the step of delineating of the method comprises chemical mechanical polishing.

An integrated circuit formed by a method of forming interconnects which comprises:

• cleaning vias formed on a wafer;
• filling vias and forming metalized bond pads;
• forming compliant, conductive bumps on the metalized bond pads;
• at least partially surrounding the compliant, conductive bumps in a supporting layer;
• delineating the compliant, conductive bumps;
• forming eutectic solder or solder alloy bumps over the compliant, conductive bumps;
• singulating integrated circuits from the wafer;
• forming compliant, conductive bumps on a printed circuit board;
• at least partially surrounding the compliant, conductive bumps in a supporting layer;
• bonding the singulated integrated circuits to the printed circuit board.

An integrated circuit formed by a method of forming interconnects which comprises:

• forming an interconnect structure that includes steps of:
• forming compliant, conductive bumps on metalized bond pads or conductors;
• enclosing the compliant, conductive bumps in a supporting layer;
• delineating the compliant, conductive bumps;
• and
• forming eutectic solder or solder alloy bumps over the compliant, conductive bumps.

An integrated circuit formed by a method of forming interconnects which comprises:

• forming an interconnect structure on one or more of an integrated circuit and a printed circuit board, wherein forming the interconnect structure includes steps of:
• forming compliant, conductive bumps on metalized bond pads or conductors;
• enclosing the compliant, conductive bumps in a supporting layer;
• delineating the compliant, conductive bumps;
• and
• forming eutectic solder or solder alloy bumps over the compliant, conductive bumps of one or more of the interconnect structures.

An interconnect structure which comprises:

• compliant, conductive bumps disposed on metalized bond pads or conductors;
• a supporting layer that, at least partially, surrounds the compliant, conductive bumps;
• and
• eutectic solder or solder alloy bumps disposed over the compliant, conductive bumps.

An interconnect structure formed on an integrated circuit on a wafer which comprises:

• compliant, conductive bumps disposed on metalized bond pads or conductors;
• a supporting layer that, at least partially, surrounds the compliant, conductive bumps an eutectic or solder alloy bumps over the compliant, conductive bumps;
• and
• trenches in the wafer on a side opposite the interconnect structure.

An integrated circuit package which comprises:

• filled vias in a singulated integrated circuit;
• metalized bond pads disposed on the vias;
• compliant, conductive bumps formed on the metalized bond pads;
• a supporting layer that, at least partially surrounds, the compliant, conductive bumps;
• eutectic solder or solder alloy bumps disposed over the compliant, conductive bumps;
• and
• wherein the singulated integrated circuits are bonded to a printed circuit board.